Operation - Linear Technology DC547A Demo Manual

operation

The conversion clock (CONV) is derived from the CLKIN
connector (J3) via a programmable divider.
The board is shipped with this divider set to divide by 64
(P0-P3). In order for this board to achieve its maximum
throughput with this jumper setting, of 125ksps, requires
that the SCLK be at 8MHz.
The programmable divider can be strapped for differ-
ent divide ratios if the required sample rate is less than
125ksps, allowing a greater percentage of the time avail-
able doing data transfer (divide ratio of less than 64), or
if a comparable SCLK rate is used, with a lower sample
rate (divide ratio greater than 64).
P0-P3 are set to code 11 (divide ratio/64) by default. The
range is 16 to 240 in increments of 16. Higher codes
produce lower ratios.
Ratio = (15-Code) • 16
To achieve the part's maximum sample rate of 150ksps
set P0-P3 to 12 (divide ratio/48) and SCLK to 7.2MHz.
The counter circuitry gates a sequence of 16 clock pulses
during CONV = 0. These can be observed on CKOUT, or
if CONV is introduced externally, (set CONV to EXT) the
clock pulses can be introduced via CLKIN (CLK to EXT,
EXT CLK to CKIN if no inversion is required).
DEMO MANUAL DC547A
Setting CLK to INT allows the use of the onboard LTC1799
oscillator. Note that this oscillator will not produce data
sheet performance unless the input frequency is quite low,
as the phase jitter of this oscillator will be transformed in
the presence of high slew rate signals into random noise.
If the amplitude of the signal falls off with increasing
frequency as many natural phenomena do, this oscillator
may produce acceptable results.
If you are undersampling, or operating the converter near
Nyquist, it is important to have a low jitter clock source.
The data output DOUT is shifted into a pair of 74HC595
serial to parallel shift registers that have output holding
registers, and tri-state outputs. If you intend to incorporate
the demo board into a prototype of a system, ENABLE-
DATA can be used to gate the outputs onto a 16-bit bus.
Alternatively, all of the signals can be produced externally,
and data can be read into a DSP via DOUT.
If you elect to use the on-board timing to clock data into a
slaved serial input port, you can use DOUT, CKOUT, along
with CONV as a busy signal or as a means of producing
a frame sync.
In the event that you do not have "coherent" signal sources
as described above, you can use windowing functions
to reduce the "leakage" effect that occurs in the Fourier
transform and get a reasonably accurate figure for SNR,
THD, SINAD and the levels of the various harmonics.
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