Operation - Linear Technology DC2077A Demo Manual

DEMO MANUAL DC2077A
PERFORMANCE SUMMARY
Table 1. Typical Demo Board Performance Summary
SYMBOL
Power Supply
V
CC
I
CC
FREQUENCY POWER GAIN
(MHZ) |S21|
100 20.2
200 20.6
240 20.6
300 20.7
400 20.6
500 20.6
600 20.6
700 20.5
800 20.5
900 20.5
1000 20.4
1100 20.3
1200 20.2
Units dB
Notes: All figures are referenced to J1 (Input Port) and J2 (Output Port).
1. Two-tone test conditions: Output power level = +2dBm/tone, tone spacing = 1MHz.
2. Single-tone test conditions: Output power level = +6dBm.
3. Small-signal noise figure.

OPERATION

The demo circuit 2077A is a high linearity, fixed gain
amplifier. It is designed for ease of use. Both the input
and output are internally matched to 50Ω single-ended
source and load impedance. Figure 2 shows the DC2077A's
S-parameters.
Figure 4 shows the demo circuit's schematic. The input and
output DC blocking capacitors (C1 and C7) are required
because this device is internally DC biased for optimal
operation. The frequency appropriate choke (L1) and the
decoupling capacitors (C3 and C4) provide the proper
DC bias to the RF output node. Only a single 5V supply is
necessary for the VCC pins on the device.
2
T = 25°C, V
A
PARAMETER
Operating Supply Range
Current Consumption
OUTPUT OUTPUT
THIRD-ORDER THIRD-ORDER
INTERCEPT INTERMODU-
1 1
POINT LATION
OIP3 OIM3
47.2 –90.4
48.0 –91.9
47.9 –91.9
47.9 –91.9
46.9 –89.9
45.0 –86.0
42.5 –81.0
39.7 –75.5
38.6 –73.1
37.1 –70.3
36.0 –68.0
35.1 –66.2
34.4 –64.8
dBm dBc
= 5V
CC
CONDITIONS
All V Pins Plus OUT
CC
Total Current
SECOND
HARMONIC THIRD HARMONIC
2
DISTORTION DISTORTION
HD2 HD3
–56.8 –96.7
–55.6 –92.9
–52.5 –106.1
–50.5 –83.1
–50.4 –77.4
–47.8 –72.6
–43.7 –64.0
–42.1 –60.7
–40.6 –63.1
–37.1 –60.4
–36.9 –55.1
–35.7 –54.5
–34.4 –53.6
dBc dBc
L2 and C6 are optional parts. These additional components
allow for further optimization to lower or wider frequency
range applications.
A parallel 62pF (C2) and 348Ω (R1) input network has
been added to ensure low frequency stability. Note that the
input stability network does degrade performance below
150MHz. Low frequency performance can be improved
by increasing the value of capacitor C2.
The T_DIODE Pin (Turret E1) can be forward biased to
ground with 1mA of current. The measured voltage will
be an indicator of the chip junction temperature (T
VALUE / UNIT
4.75V to 5.25V
95mA
OUTPUT 1DB
COMPRESSION
2
POINT NOISE FIGURE
P1DB
23.2
22.4
22.0
21.8
21.7
21.8
21.7
21.4
21.4
21.1
20.8
20.4
20.3
dBm
3
NF
3.2
2.7
2.7
2.8
2.8
2.9
3.1
3.3
3.4
3.7
3.8
3.9
4.1
dB
).
J
dc2077af