Icom IC-730 Instruction Manual page 23

The IC-730 has a PA protection circuit which detects
reflected power, and ALC condition.
If some problem occurs, such as mismatching of the
antenna, the circuit reduces the driving power to the final
power transistors, and protects them.
6 - 5 DET UNIT
Composed IF amplifier, AGC circuit, AM detector, SSB/CW
detector, modulation circuit and BFO circuit.
During receive, SSB or CW signal from the MAIN unit, is
directly fed to a product detector IC with respective BFO
signal of each mode.
The detected AF signal is fed to a buffer amplifier, then an
active low-pass filter and cut out high frequency component,
then sent the AF power amplifier in the MAIN unit.
AM signal from the MAIN unit, is fed to an IF amplifier, then
an AM detector. The detected A F signal is fed to a buffer
amplifier, then the same active low-pass filter that for SSB
or CW signal.
A part of the amplified IF signals is rectified for AGC, and
drives AGC DC amplifier. The AGC voltage is superimposed
with the RF GAIN control voltage, and applied to the IF
amplifiers.
During transmit, the AF signal from MIC amplifier in the
MAIN unit, is applied to the balanced modulator IC with the
BFO signal, the same as receive, and produced a double
sideband suppressed carrier signal. This DSB signal is sent
ND
to the 2 IF unit and changed into an SSB signal.
In AM or CW mode, the balanced modulator is unbalanced,
and puts out a carrier for CW or AM signal. This signal is
nd
sent to the 2 IF unit the same as SSB.
6 - 6 PA UNIT
This unit is made up of three stage wideband amplifiers,
negative feedback circuits for giving a gain flatness
response across the bands, and thermal switch that monitor
the temperature of the final transistors and control the speed
of the cooling fan. The signal from the RF unit is applied this
unit and amplified to 100 watts.
6 - 7 LOGIC UNIT
This unit is composed of an incorporated CPU for treating
data such as up/down signal detection control, the dial lock
control circuit, the tuning rate circuit, and the I/0 control
circuit.
The dial clock signals are generated by the photo-chopper
directly connected to the tuning knob. The up/down cont-
rol circuit detects the rotating direction of the tuning knob,
and puts out the up/down control signal for the CPU.
The CPU is a 4-bit microcomputer which has a program to
control the set. The CPU's function are determined by the
input signals, such as the dial clock signal, up/down signal
and the signals from the function switches, and the CPU
puts out signals to control the operating frequency, tuning
steps, display, and so on.
6 - 8 DISPLAY UNIT
Composed of a luminescent display tube, display control
circuit and DC-DC converter.
The operating frequency data from the CPU in the LOGIC
unit, are applied to the display control IC, and it puts out 7
segment data and digit control signals and displays operat-
ing frequency. The DC-DC converter produces a filament
voltage and high voltage for display tube, and -5V for IC's
and AGC circuit.
6 - 9 PLL UNIT
This unit is composed of a mixed down type Phase-Locked
Loop and a high speed 1/10 divider. The local oscillator of
the PLL consists of a 13.66MHz crystal oscillator and two
stage triplers, and puts out 123MHz signal.
The VCO oscillates 132MHz ~ 139MHz, and is mixed with
123MHz local oscillator signal, and mixed down to 9MHz ~
16MHz. This signal is fed to a programmable divider in the
PLL IC and divided to 10KHz and compared with 10KHz
reference frequency which is divided from 9MHz, crystal
oscillator, and locked up to the reference frequency. The
programmable divider is controlled by the frequency data
from the CPU.
The VCO output is led to the 1/10 divider and the resulting
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