Texas Instruments DLP801XE Manual
Texas Instruments DLP801XE Manual

Texas Instruments DLP801XE Manual

0.8 4k+ digital micromirror device
Table of Contents

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1 Features

0.8-inch diagonal micromirror array
– 4K+ (3840 × 2400) display resolution
– 9.0-µm micromirror pitch
– ±14.5° micromirror tilt (relative to flat surface)
– Corner illumination
Supports high optical power density for high-
brightness large venue displays
2
– Up to 40W/cm
total optical power density
2xLVDS input data bus
Supports 4K+ up to 60 Hz
Laser-phosphor, and RGB laser supported by
DLPC4420 display controller, DLPA100 power
management and motor driver IC

2 Applications

Large venue projector
Smart projector
Enterprise projector
Digital signage
DLPC4420
Display Controller
DLPC4420
Display Controller
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DLP801XE 0.8 4K+ Digital Micromirror Device
SCRTL_C
2xLVDS Bus C Data Pairs
DCLK_C
SCRTL_D
2xLVDS Bus D Data Pairs
DCLK_D
SPI
DLPA300 Control
DMD POWER En
2
I
C
SCRTL_A
2xLVDS Bus A Data Pairs
DCLK_A
SCRTL_B
2xLVDS Bus B Data Pairs
DCLK_B
Simplified Application
DLPS243B – OCTOBER 2022 – REVISED SEPTEMBER 2023

3 Description

The DLP801XE digital micromirror device (DMD) is
a digitally controlled micro-electromechanical system
(MEMS) spatial light modulator (SLM) that enables
bright 4K+ solid-state illuminated display systems.
The TI DLP
®
0.8-inch 4K+ chipset comprises the
DMD, two DLPC4420 display controllers,
micromirror driver, and
driver. The compact physical size of the chipset
provides a complete system that enables small form
factor 4K+ displays with solid-state illumination.
To help accelerate the design cycle, the DMD
ecosystem includes established resources, which
include
production ready optical
module
manufacturers, and
To learn more about how to start designing with the
DMD, visit the
Getting Started with TI DLP display
technology
page.
Device Information
(1)
PART NUMBER
DLP801XE
FYV (350)
(1)
For all available packages, see the orderable addendum at
the end of the data sheet.
16
16
DPLA300
MBRST
Micromirror
-16.5 V
Driver
15
12 V
10 V
VREG
1.8 V
VREG
3.3 V
Temperature
TMP411
2
16
16
DLP801XE
DLPA300
DLPA100
power and motor
modules,
design
houses.
PACKAGE SIZE
PACKAGE
(NOM)
35.0 mm × 32.2 mm
DLP801XE
2xLVDS DMD
optical

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Summary of Contents for Texas Instruments DLP801XE

  • Page 1: Features

    DLP801XE 0.8 4K+ Digital Micromirror Device 1 Features 3 Description • 0.8-inch diagonal micromirror array The DLP801XE digital micromirror device (DMD) is a digitally controlled micro-electromechanical system – 4K+ (3840 × 2400) display resolution (MEMS) spatial light modulator (SLM) that enables – 9.0-µm micromirror pitch bright 4K+ solid-state illuminated display systems.
  • Page 2: Table Of Contents

    Window Aperture Illumination Overfill Calculation .............27 Changes from Revision * (October 2022) to Revision A (March 2023) Page • Added t ..............................14 SKEW_A2B • Updated Figure 6-8 ............................16 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: DLP801XE...
  • Page 3: Pin Configuration And Functions

    DLP801XE www.ti.com DLPS243B – OCTOBER 2022 – REVISED SEPTEMBER 2023 5 Pin Configuration and Functions Figure 5-1. FYV Package (350-Pin) Bottom View Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: DLP801XE...
  • Page 4 D_AN(15) High-speed differential pair Differential 100 Ω D_AP(15) DCLK_AN High-speed differential pair Differential 100 Ω DCLK_AP SCTRL_AN High-speed differential pair Differential 100 Ω SCTRL_AP LVDS BUS B Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: DLP801XE...
  • Page 5 D_BN(15) High-speed differential pair Differential 100 Ω D_BP(15) DCLK_BN High-speed differential pair Differential 100 Ω DCLK_BP SCTRL_BN High-speed differential pair Differential 100 Ω SCTRL_BP LVDS BUS C Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: DLP801XE...
  • Page 6 D_CN(15) High-speed differential pair Differential 100 Ω D_CP(15) DCLK_CN High-speed differential pair Differential 100 Ω DCLK_CP SCTRL_CN High-speed differential pair Differential 100 Ω SCTRL_CP LVDS BUS D Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: DLP801XE...
  • Page 7 LVCMOS Internal pulldown SCPENZ Serial Communications Port Enable LVCMOS Internal pulldown SCPDO Serial Communications Port Output LVCMOS Internal pulldown OTHER SIGNALS DMD_PWRDNZ Chip–Level ResetZ LVCMOS Internal pulldown Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: DLP801XE...
  • Page 8 M3, M4, M25, N1, Low-voltage CMOS core supply N25, P1, R2, V1, V2, W8, W19, W20, W21, W22, X10, X12, X19, X22, Y1, Z1, Z2, AA2, AA5, Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: DLP801XE...
  • Page 9 Y2, Y9, Y20, Y22, Y24, Z4, Z7, Z11, Z14, Z17, Z20, Z22, I = Input, O = Output, P = Power, G = Ground, NC = No Connect Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: DLP801XE...
  • Page 10: Specifications

    JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: DLP801XE...
  • Page 11: Recommended Operating Conditions

    Illumination power at wavelengths ≥ 410 nm and ≤ 475 nm 12.8 W/cm (17) (18) Illumination power at wavelengths ≥ 410 nm and ≤ 440 nm W/cm BLU1 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: DLP801XE...
  • Page 12 (T ARRAY (18) To calculate see Micromirror Power Density Calculation. (19) Multichip architectures must use the same DMD device (DLP801XE) for all DMDs in the product. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: DLP801XE...
  • Page 13 Figure 6-1. Maximum Recommended Array Temperature—Derating Curve 0.50 mm Critical area on window aperture Window Array 13.325 mm Window Aperture 18.763 Window Aperture Window Figure 6-2. Illumination Overfill Diagram—Critical Area Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: DLP801XE...
  • Page 14: Thermal Information

    Time between falling edge of SCPCLK and the rising edge of SCP_POS_EN µs SCPENZ Time required for SCP output buffer to recover after SCPENZ (from SCP_OUT_EN tri-state). SCPENZ inactive pulse width (high-level) SCP_PW_ENZ scpclk Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: DLP801XE...
  • Page 15 Channel B (Bus B) includes the following LVDS pairs: DCLK_B, SCTRL_B, and D_B. Channel C (Bus C) includes the following LVDS pairs: DCLK_C, SCTRL_C, and D_C Channel D (Bus D) includes the following LVDS pairs: DCLK_D, SCTRL_D, and D_D. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: DLP801XE...
  • Page 16: Updated Figure 6-8

    SCPCLK rising±edge launch for SCPDO SCPENZ SCP_DS SCP_DH SCPDI SCPCLK SCP_PD SCPDO Figure 6-3. SCP Timing Parameters SCPCLK, SCPDI, SCPDO, SCPENZ 100% Time Figure 6-4. SCP Rise and Fall Times Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: DLP801XE...
  • Page 17 LVDS min Figure 6-5. LVDS Waveform Parameters DCLK_CN, DCLK_CP, D_CN(0:15), D_CP(0:15), SCRTL_CN, SCTRL_CP, DCLK_DN, DCLK_DP, D_DN(0:15), D_DP(0:15), SCRTL_DN, SCTRL_DP 100% Time Figure 6-6. LVDS Rise and Fall Times Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: DLP801XE...
  • Page 18: System Mounting Interface Loads

    6.8 System Mounting Interface Loads PARAMETER UNIT When loads are applied on both electrical and thermal interface areas Maximum load to be applied to the electrical interface area Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: DLP801XE...
  • Page 19 Maximum load to be applied to the thermal interface area The load must be uniformly applied in the corresponding areas shown in Figure 6-9. Electrical Interface Area Thermal Interface Area Figure 6-9. System Mounting Interface Loads Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: DLP801XE...
  • Page 20: Micromirror Array Physical Characteristics

    N ± 1 Off-State M x P Light Path Pond Of Micromirrors (POM) omitted for clarity. Details omitted for clarity. Not to scale. Figure 6-10. Micromirror Array Physical Characteristics Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: DLP801XE...
  • Page 21: Micromirror Array Optical Characteristics

    (15) Unstable pixel definition: A single pixel or mirror that does not operate in sequence with parameters loaded into memory. The unstable pixel appears to be flickering asynchronously with the image. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: DLP801XE...
  • Page 22: Window Characteristics

    Index 6.12 Chipset Component Usage Specification Reliable function and operation of the DLP801XE DMD requires that it be used in conjunction with the other components of the applicable DLP chipset, including those components that contain or implement TI DMD Submit Document Feedback Copyright ©...
  • Page 23: Detailed Description

    DLPA100 power management and motor driver. For reliable operation, the DLP801XE DMD must always be used with the DLP display controller and the power and motor driver specified in the chipset. 7.2 Functional Block Diagram Channel A and C Interface...
  • Page 24: Feature Description

    The DLP801XE has a 14.5° tilt angle which corresponds to the f/2.0 numerical aperture. The micromirror tilt angle defines DMD capability to separate the "ON"...
  • Page 25: Micromirror Array Temperature Calculation

    + (Q × R ARRAY CERAMIC ARRAY ARRAY-TO-CERAMIC ARRAY ELECTRICAL ILLUMINATION where • = Computed array temperature (°C) ARRAY • = Measured ceramic temperature (°C) (TP1 location) CERAMIC Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: DLP801XE...
  • Page 26: Micromirror Power Density Calculation

    = illumination area on the DMD (cm • = total incident optical power on DMD (W) (measured) INCIDENT • = area of the array (cm ) (data sheet) ARRAY Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: DLP801XE...
  • Page 27: Window Aperture Illumination Overfill Calculation

    The amount of optical overfill on the critical area of the window aperture cannot be measured directly. For systems with uniform illumination on the array the amount is determined using the total measured incident Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: DLP801XE...
  • Page 28 (22) INCIDENT = 0.312% (optical model) (23) AP_ILL_RATIO = 25% (optical model) (24) CA_RATIO Length of the window aperture for critical area = 1.8763 (data sheet) (25) Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: DLP801XE...
  • Page 29: Micromirror Landed-On/Landed-Off Duty Cycle

    For example, in the simplest case, when displaying pure-white on a given pixel for a given time period, that pixel operates under a 100/0 landed duty cycle during that time period. Likewise, when displaying pure-black, the pixel operates under a 0/100 landed duty cycle. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: DLP801XE...
  • Page 30 CYCLE PERCENTAGE GREEN BLUE Table 7-3. Example Landed Duty Cycle for Full-Color SCALE VALUE LANDED DUTY CYCLE GREEN BLUE 0/100 100% 30/70 100% 50/50 100% 20/80 6/94 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: DLP801XE...
  • Page 31 Consideration must also be given to any image processing which occurs before the DLPC4420 display controller. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: DLP801XE...
  • Page 32: Application And Implementation

    DMD power-up and power-down sequencing is strictly controlled by the DLPC4420 display controller through the DLPA300. Refer to Power Supply Recommendations for power-up and power-down specifications. For reliable operation, the DLP801XE DMD must always be used with two DLPC4420 display controllers, a DLPA100...
  • Page 33 Flash 1.15V ADDR DATA FPGA 1.5V Voltage 2.5V DLP Chipset Components Regulators 12 V 3.3V Flash DDR VTT and REF Figure 8-1. Typical 4K+ RGB Laser Application Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: DLP801XE...
  • Page 34 The display system uses the DLP801XE DMD as the core imaging device and contains a 0.8-inch array of micromirrors. The DLPC4420 display controller is the digital interface between the DMD and the rest of the system, taking digital input from front end receiver and driving the DMD over a high-speed LVDS interface.
  • Page 35: Temperature Sensor Diode

    8-4. The software application contains functions to configure the TMP411 to read the DLP801XE DMD temperature sensor diode. This data can be leveraged by the customer to incorporate additional functionality in the overall system design such as adjusting illumination, fan speeds, etc. All communication between the...
  • Page 36 TI reference design for suggested component values for R1, R2, R3, R4, and C1. R5 = 0 Ω. R6 = 0 Ω. Place 0-Ω resistors close to the DMD package pins. Figure 8-4. TMP411 Sample Schematic Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: DLP801XE...
  • Page 37: Power Supply Recommendations

    Power supply slew rates during power-down are flexible, provided that the transient voltage levels follow the requirements listed in Section 6.1 and in Section 6.4. • During power-down, LVCMOS input pins must be less than specified in Section 6.4. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: DLP801XE...
  • Page 38 VDD must remain high until after VCC2 goes low. To prevent excess current, the supply voltage delta |VDDI – VDD| must be less than specified limit in Section 6.4. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: DLP801XE...
  • Page 39: Layout

    10 Layout 10.1 Layout Guidelines The DLP801XE DMD is part of a chipset that is controlled by the two DLPC4420 display controllers in conjunction with the DLP300 micromirror driver and the DLPA100 power and motor driver. These guidelines are targeted at designing a PCB board with the DLP801XE DMD. The DLP801XE DMD board is a high-speed multi-layer PCB, with primarily high-speed digital logic utilizing dual edge clock rates up to 400MHz for DMD LVDS signals.
  • Page 40 Maximize trace width to connecting pin VDD, VDDI Maximize trace width to connecting pin MBRST(0,14) Use 10 mil etch to connect all signals/voltages from DLPA300 to DLP801XE VCC2 Create mini plane from Voltage regulator to DLP801XE Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated...
  • Page 41: Device And Documentation Support

    (Part Number and Serial Number) DLP801XE xc FYV GHXXXXX LLLLLLM Part 1 of Serial Number Part 2 of Serial Number (7 characters) (7 characters) Figure 11-2. DMD Marking Locations Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: DLP801XE...
  • Page 42: Documentation Support

    All trademarks are the property of their respective owners. 11.8 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
  • Page 43: Package Option Addendum

    Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. space Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links:...
  • Page 48 TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2023, Texas Instruments Incorporated...

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