Omron CP1L - 12-2007 Operation Manual page 544

Auxiliary Area Allocations by Function
Name
High-speed Counter PV
High-speed Range 1
Counter Range
Range 2
Comparison
Condition Met
Range 3
Flags
Range 4
Range 5
Range 6
Range 7
Range 8
High-speed Counter Com-
parison In-progress Flag
High-speed Counter Over-
flow/Underflow Flag
High-speed Counter
Count Direction
High-speed Counter
Reset Bit
High-speed Counter Gate
Bit
Built-in Outputs
Pulse Outputs 0, 1
Item
Pulse Output PV Leftmost 4 digits
Rightmost 4 digits
Pulse Output Accel/Decel Flag
Pulse Output Overflow/Underflow Flag
Pulse Output, Output Amount Set Flag
Pulse Output, Output Completed Flag
Pulse Output, Output In-progress Flag
Pulse Output No-origin Flag
Pulse Output At-origin Flag
Pulse Output, Output Stopped Error Flag
PWM Output, Output In-progress Flag
Description
Contains the PV of the high-speed counter.
These flags indicate whether the PV is within the
specified ranges when the high-speed counter is
being operated in range-comparison mode.
OFF: PV not in range
ON: PV in range
This flag indicates whether a comparison operation
is being executed for the high-speed counter.
OFF: Stopped.
ON: Being executed.
This flag indicates when an overflow or underflow
has occurred in the high-speed counter PV. (Used
with the linear mode counting range only.)
OFF: Normal
ON: Overflow or underflow
This flag indicates whether the high-speed counter
is currently being incremented or decremented. The
counter PV for the current cycle is compared with
the PLC in last cycle to determine the direction.
OFF: Decrementing
ON: Incrementing
When the reset method is set to Phase-Z signal +
Software reset, the corresponding high-speed
counter's PV will be reset if the phase-Z signal is
received while this bit is ON.
When the reset method is set to a software reset,
the corresponding high-speed counter's PV will be
reset in the cycle when this bit goes ON.
When a counter's Gate Bit is ON, the counter's PV
will not be changed even if pulse inputs are received
for the counter.
When the bit is turned OFF again, counting will
restart and the high-speed counter's PV will be
updated.
When the reset method is set to Phase-Z signal +
Software reset, the Gate Bit is disabled while the
corresponding Reset Bit is ON.
Pulse output
0
A277
A276
A280.00
A280.01
A280.02
A280.03
A280.04
A280.05
A280.06
A280.07
A283.00
Read/Write
Read-only
Read-only
Read-only
Read-only
Read-only
Read/Write
Read/Write
Pulse output
1
A279
A278
A281.00
A281.01
A281.02
A281.03
A281.04
A281.05
A281.06
A281.07
A283.08
Appendix C
Updated
• Cleared when power is turned ON.
• Cleared when operation starts.
• Updated each cycle during oversee-
ing process.
• Updated when PRV(881) instruction
is executed for the corresponding
counter.
• Cleared when power is turned ON.
• Cleared when operation starts.
• Cleared when range comparison
table is registered.
• Updated each cycle during oversee-
ing process.
• Updated when PRV(881) instruction
is executed to read range compari-
son results.
• Cleared when power is turned ON.
• Cleared when operation starts.
• Updated when comparison operation
starts or stops.
• Cleared when power is turned ON.
• Cleared when operation starts.
• Cleared when the PV is changed.
• Updated when an overflow or under-
flow occurs.
• Setting used for high-speed counter,
valid during counter operation.
• Cleared when power is turned ON.
• Cleared when power is turned ON.
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