NEC uPD70F3744 Manuals

Manuals and User Guides for NEC uPD70F3744. We have 1 NEC uPD70F3744 manual available for free PDF download: Hardware User Manual

NEC uPD70F3744 Hardware User Manual (911 pages)

32-bit Single-Chip Microcontrollers

Brand: NEC | Category: Microcontrollers | Size: 7 MB

Table of Contents
9
Chapter 1 Introduction

19
- General
  19
- Features
  21
- Application Fields
  22
- Ordering Information
  22
- Pin Configuration (Top View)
  23
- Function Block Configuration
  25
- Internal Block Diagram
  25
- Internal Units
  26
Chapter 2 Pin Functions

29
Chapter 3 Cpu Function

46
- Features
  46
- CPU Register Set
  47
- Program Register Set
  48
- System Register Set
  49
- Operation Modes
  55
- Specifying Operation Mode
  55
- Address Space
  56
- CPU Address Space
  56
- Wraparound of CPU Address Space
  57
- Memory Map
  58
- Areas
  60
- Recommended Use of Address Space
  65
- Peripheral I/O Registers
  68
- Special Registers
  80
- Cautions
  84
Chapter 4 Port Functions

87
- Features
  87
- Basic Port Configuration
  87
- Port Configuration
  88
- Port 0
  93
- Port 1
  97
- Port 3
  98
- Port 4
  104
- Port 5
  106
- Port 6
  110
- Port 7
  114
- Port 8
  116
- Port 9
  118
- Port CD
  126
- Port CM
  127
- Port CS
  129
- Port CT
  131
- Port DH
  133
- Port DL
  135
- Block Diagrams
  138
- Port Register Settings When Alternate Function Is Used
  170
- Cautions
  179
- Cautions on Setting Port Pins
  179
- Cautions on Bit Manipulation Instruction for Port N Register (Pn)
  182
- Cautions on On-Chip Debug Pins
  183
- Cautions on P05/INTP2/DRST Pin
  183
- Cautions on P53 Pin When Power Is Turned on
  183
- Hysteresis Characteristics
  183
Chapter 5 Bus Control Function

184
- Features
  184
- Bus Control Pins
  185
- Pin Status When Internal ROM, Internal RAM, or On-Chip Peripheral I/O Is Accessed
  185
- Pin Status in each Operation Mode
  185
- Memory Block Function
  186
- External Bus Interface Mode Control Function
  187
- Bus Access
  188
- Number of Clocks for Access
  188
- Bus Size Setting Function
  188
- Access by Bus Size
  189
- Wait Function
  196
- Programmable Wait Function
  196
- External Wait Function
  197
- Relationship between Programmable Wait and External Wait
  198
- Programmable Address Wait Function
  199
- Idle State Insertion Function
  200
- Bus Hold Function
  201
- Functional Outline
  201
- Bus Hold Procedure
  202
- Operation in Power Save Mode
  202
- Bus Priority
  203
- Bus Timing
  204
Chapter 6 Clock Generation Function

210
- Overview
  210
- Configuration
  211
- Registers
  213
- Operation
  218
- Operation of each Clock
  218
- Clock Output Function
  218
- PLL Function
  219
- Overview
  219
- Registers
  219
- Usage
  222
Chapter 7 16-Bit Timer/Event Counter P (Tmp)

223
- Overview
  223
- Functions
  223
- Configuration
  224
- Registers
  226
- Operation
  238
- Interval Timer Mode (Tpnmd2 to Tpnmd0 Bits = 000)
  239
- External Event Count Mode (Tpnmd2 to Tpnmd0 Bits = 001)
  249
- External Trigger Pulse Output Mode (Tpnmd2 to Tpnmd0 Bits = 010)
  257
- One-Shot Pulse Output Mode (Tpnmd2 to Tpnmd0 Bits = 011)
  269
- PWM Output Mode (Tpnmd2 to Tpnmd0 Bits = 100)
  276
- Free-Running Timer Mode (Tpnmd2 to Tpnmd0 Bits = 101)
  285
- Pulse Width Measurement Mode (Tpnmd2 to Tpnmd0 Bits = 110)
  302
- Timer Output Operations
  308
- Selector Function
  309
- Cautions
  311
Chapter 8 16-Bit Timer/Event Counter Q (Tmq)

312
- Overview
  312
- Functions
  312
- Configuration
  313
- Registers
  315
- Operation
  331
- Interval Timer Mode (TQ0MD2 to TQ0MD0 Bits = 000)
  332
- External Event Count Mode (TQ0MD2 to TQ0MD0 Bits = 001)
  341
- External Trigger Pulse Output Mode (TQ0MD2 to TQ0MD0 Bits = 010)
  350
- One-Shot Pulse Output Mode (TQ0MD2 to TQ0MD0 Bits = 011)
  363
- PWM Output Mode (TQ0MD2 to TQ0MD0 Bits = 100)
  372
- Free-Running Timer Mode (TQ0MD2 to TQ0MD0 Bits = 101)
  383
- Pulse Width Measurement Mode (TQ0MD2 to TQ0MD0 Bits = 110)
  403
- Timer Output Operations
  409
- Cautions
  410
Chapter 9 16-Bit Interval Timer M (Tmm)

411
- Overview
  411
- Configuration
  412
- Register
  413
- Operation
  414
- Interval Timer Mode
  414
- Cautions
  418
Chapter 10 Watch Timer Functions

419
- Functions
  419
- Configuration
  420
- Control Registers
  422
- Operation
  426
- Operation as Watch Timer
  426
- Operation as Interval Timer
  427
- Cautions
  428
Chapter 11 Functions of Watchdog Timer 2

429
- Functions
  429
- Configuration
  430
- Registers
  431
- Operation
  433
Chapter 12 Real-Time Output Function (Rto)

434
- Function
  434
- Configuration
  435
- Registers
  437
- Operation
  439
- Usage
  440
- Cautions
  440
Chapter 13 A/D Converter

441
- Overview
  441
- Functions
  441
- Configuration
  442
- Registers
  445
- Operation
  456
- Basic Operation
  456
- Conversion Operation Timing
  457
- Trigger Mode
  458
- Operation Mode
  460
- Power-Fail Compare Mode
  464
- Cautions
  469
- How to Read A/D Converter Characteristics Table
  473
Chapter 14 D/A Converter

477
- Functions
  477
- Configuration
  477
- Registers
  478
- Operation
  480
- Operation in Normal Mode
  480
- Operation in Real-Time Output Mode
  480
- Cautions
  481
Chapter 15 Asynchronous Serial Interface a (Uarta)

482
- Mode Switching of UARTA and Other Serial Interfaces
  482
- CSIB4 and UARTA0 Mode Switching
  482
- UARTA2 and I 2 C00 Mode Switching
  483
- UARTA1 and I 2 C02 Mode Switching
  484
- Features
  485
- Configuration
  486
- Registers
  488
- Interrupt Request Signals
  494
- Operation
  495
- Data Format
  495
- SBF Transmission/Reception Format
  497
- SBF Transmission
  499
- SBF Reception
  500
- UART Transmission
  502
- Continuous Transmission Procedure
  503
- UART Reception
  505
- Reception Errors
  506
- Parity Types and Operations
  508
- Receive Data Noise Filter
  509
- Dedicated Baud Rate Generator
  510
- Cautions
  518
Chapter 16 3-Wire Variable-Length Serial I/O (Csib)

519
Chapter 17 I C Bus

568
- Mode Switching of I 2 C Bus and Other Serial Interfaces
  568
- UARTA2 and I 2 C00 Mode Switching
  568
- CSIB0 and I 2 C01 Mode Switching
  569
- UARTA1 and I 2 C02 Mode Switching
  570
- Features
  571
- Configuration
  572
- Registers
  576
- I C Bus Mode Functions
  592
- Pin Configuration
  592
- I C Bus Definitions and Control Methods
  593
- Start Condition
  593
- Addresses
  594
- Transfer Direction Specification
  595
- Ack
  596
- Stop Condition
  597
- Wait State
  598
- Wait State Cancellation Method
  600
- I C Interrupt Request Signals (Intiicn)
  601
- Master Device Operation
  601
- Slave Device Operation (When Receiving Slave Address Data (Address Match))
  604
- Slave Device Operation (When Receiving Extension Code)
  608
- Operation Without Communication
  612
- Arbitration Loss Operation (Operation as Slave after Arbitration Loss)
  612
- Operation When Arbitration Loss Occurs (no Communication after Arbitration Loss)
  614
- Interrupt Request Signal (Intiicn) Generation Timing and Wait Control
  621
- Address Match Detection Method
  623
- Error Detection
  623
- Extension Code
  623
- Arbitration
  624
- Wakeup Function
  625
- Communication Reservation
  626
- When Communication Reservation Function Is Enabled (Iicfn.iicrsvn Bit = 0)
  626
- When Communication Reservation Function Is Disabled (Iicfn.iicrsvn Bit = 1)
  630
- Cautions
  631
- Communication Operations
  632
- Master Operation in Single Master System
  633
- Master Operation in Multimaster System
  634
- Slave Operation
  637
- Timing of Data Communication
  640
Chapter 18 Dma Function (Dma Controller)

647
- Features
  647
- Configuration
  648
- Registers
  649
- Transfer Targets
  656
- Transfer Modes
  657
- Transfer Types
  657
- DMA Channel Priorities
  658
- Time Related to DMA Transfer
  658
- DMA Transfer Start Factors
  659
- DMA Abort Factors
  660
- End of DMA Transfer
  660
- Operation Timing
  660
- Cautions
  665
Chapter 19 Interrupt/Exception Processing Function

670
- Features
  670
- Non-Maskable Interrupts
  674
- Operation
  676
- Restore
  677
- NP Flag
  678
- Maskable Interrupts
  679
- Operation
  679
- Restore
  681
- Priorities of Maskable Interrupts
  682
- Interrupt Control Register (Xxicn)
  686
- Interrupt Mask Registers 0 to 4 (IMR0 to IMR4)
  688
- In-Service Priority Register (ISPR)
  690
- ID Flag
  691
- Watchdog Timer Mode Register 2 (WDTM2)
  691
- Software Exception
  692
- Operation
  692
- Restore
  693
- EP Flag
  694
- Exception Trap
  695
- Illegal Opcode Definition
  695
- Debug Trap
  697
- External Interrupt Request Input Pins (NMI and INTP0 to INTP8)
  699
- Noise Elimination
  699
- Edge Detection
  699
- Interrupt Acknowledge Time of CPU
  705
- Periods in Which Interrupts Are Not Acknowledged by CPU
  706
- Cautions
  706
Chapter 20 Key Interrupt Function

707
- Function
  707
- Register
  708
- Cautions
  708
Chapter 21 Standby Function

709
- Overview
  709
- Registers
  711
- HALT Mode
  714
- Setting and Operation Status
  714
- Releasing HALT Mode
  714
- IDLE1 Mode
  716
- Setting and Operation Status
  716
- Releasing IDLE1 Mode
  716
- IDLE2 Mode
  718
- Setting and Operation Status
  718
- Releasing IDLE2 Mode
  718
- Securing Setup Time When Releasing IDLE2 Mode
  720
- STOP Mode
  721
- Setting and Operation Status
  721
- Releasing STOP Mode
  721
- Securing Oscillation Stabilization Time When Releasing STOP Mode
  724
- Subclock Operation Mode
  725
- Setting and Operation Status
  725
- Releasing Subclock Operation Mode
  725
- Sub-IDLE Mode
  727
- Setting and Operation Status
  727
- Releasing Sub-IDLE Mode
  727
Chapter 22 Reset Functions

729
- Overview
  729
- Registers to Check Reset Source
  730
- Operation
  731
- Reset Operation Via RESET Pin
  731
- Reset Operation by Watchdog Timer 2
  733
- Reset Operation by Low-Voltage Detector
  735
- Operation after Reset Release
  736
- Reset Function Operation Flow
  737
Chapter 23 Clock Monitor

738
- Functions
  738
- Configuration
  738
- Register
  739
- Operation
  740
Chapter 24 Low-Voltage Detector (Lvi)

743
- Functions
  743
- Configuration
  743
- Registers
  744
- Operation
  746
- To Use for Internal Reset Signal
  746
- To Use for Interrupt
  747
- RAM Retention Voltage Detection Operation
  748
- Emulation Function
  749
Chapter 25 Crc Function

750
- Functions
  750
- Configuration
  750
- Registers
  751
- Operation
  752
- Usage Method
  753
Chapter 26 Regulator

755
- Overview
  755
- Operation
  756
Chapter 27 Flash Memory

757
- Features
  757
- Memory Configuration
  758
- Functional Outline
  760
- Rewriting by Dedicated Flash Programmer
  763
- Programming Environment
  763
- Communication Mode
  764
- Flash Memory Control
  770
- Selection of Communication Mode
  771
- Communication Commands
  772
- Pin Connection
  773
- Rewriting by Self Programming
  777
- Overview
  777
- Features
  778
- Standard Self Programming Flow
  779
- Flash Functions
  780
- Pin Processing
  780
- Internal Resources Used
  781
Chapter 28 On-Chip Debug Function

782
- Debugging with DCU
  783
- Connection Circuit Example
  783
- Interface Signals
  783
- Maskable Functions
  785
- Register
  785
- Operation
  787
- Cautions
  787
- Debugging Without Using DCU
  788
- Circuit Connection Examples
  788
- Maskable Functions
  789
- Securement of User Resources
  790
- Cautions
  796
- ROM Security Function
  798
- Security ID
  798
- Setting
  799
Chapter 29 Electrical Specifications

801
Chapter 30 Package Drawing

836
Chapter 31 Recommended Soldering Conditions

837
Appendix A Development Tools

838
- Software Package
  840
- Language Processing Software
  840
- Control Software
  840
- Debugging Tools (Hardware)
  841
- When Using IECUBE QB-V850ESSX2
  841
- When Using MINICUBE QB-V850MINI
  843
- When Using MINICUBE2 QB-MINI2
  844
- Debugging Tools (Software)
  845
- Embedded Software
  846
- Flash Memory Writing Tools
  847
Appendix B Major Differences between V850Es/Jj3 and V850Es/Jj2

848
Appendix C Register Index

850
Appendix D Instruction Set List

862
- Conventions
  862
- Instruction Set (in Alphabetical Order)
  865
Appendix E List of Cautions

872
Appendix F Revision History

909
- Major Revisions in this Edition
  909
- Revision History of Previous Editions
  910

NEC Categories

Monitor

Projector Server

Telephone Computer Hardware

More NEC Manuals

NEC uPD70F3744 Manuals

NEC uPD70F3744 Hardware User Manual (911 pages)

Table of Contents

Chapter 1 Introduction

Chapter 2 Pin Functions

Chapter 3 Cpu Function

Chapter 4 Port Functions

Chapter 5 Bus Control Function

Chapter 6 Clock Generation Function

Chapter 7 16-Bit Timer/Event Counter P (Tmp)

Chapter 8 16-Bit Timer/Event Counter Q (Tmq)

Chapter 9 16-Bit Interval Timer M (Tmm)

Chapter 10 Watch Timer Functions

Chapter 11 Functions of Watchdog Timer 2

Chapter 12 Real-Time Output Function (Rto)

Chapter 13 A/D Converter

Chapter 14 D/A Converter

Chapter 15 Asynchronous Serial Interface a (Uarta)

Chapter 16 3-Wire Variable-Length Serial I/O (Csib)

Chapter 17 I C Bus

Chapter 18 Dma Function (Dma Controller)

Chapter 19 Interrupt/Exception Processing Function

Chapter 20 Key Interrupt Function

Chapter 21 Standby Function

Chapter 22 Reset Functions

Chapter 23 Clock Monitor

Chapter 24 Low-Voltage Detector (Lvi)

Chapter 25 Crc Function

Chapter 26 Regulator

Chapter 27 Flash Memory

Chapter 28 On-Chip Debug Function

Chapter 29 Electrical Specifications

Chapter 30 Package Drawing

Chapter 31 Recommended Soldering Conditions

Appendix A Development Tools

Appendix B Major Differences between V850Es/Jj3 and V850Es/Jj2

Appendix C Register Index

Appendix D Instruction Set List

Appendix E List of Cautions

Appendix F Revision History

Related Products

NEC Categories