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2-34
Basic Digital Circuits (see Fig. 2.13)
2 . 6 . 2 .
The type of logic used is T T L and the supply voltage
The logic levels used are defined as follows:
-
(H) constitutes an input between 2...5 V and an output between 2.4
a high level
-
level ( L ) constitutes an input between 0...0,8 V and an output of between 0...0,4 V .
a low
The following types of logic circuit elements are used this instrument:
-
AND-gate:
-
NAND-GATE: the output is only L if a l l the inputs are H. Therefore, if one input is L the
OR-gate:
-
NOR-gate:
-
-
D-FLIP-FLOP: One integrated circuit incorporates
- JK FLIP-FLOP: One I C contains two flip-flops. Each flip-flop has an output (pin 5 or 9) and an inverted
In this gate, the output is only H if all the inputs are H. Therefore, if one input is low, the
s t a t e of the other inputs i s irrelevant and the output i s
inputs is irrelevant and the output is H.
the output i s only L i f all inputs are L. I f one input i s H, then the state of the other inputs
is irrelevant and the output is H.
the output i s only H if all inputs are L. Therefore, if one input is H, the s t a t e of the other
inputs is irrelevant and the output i s L.
Each flip-flop has an output (pin 5 or 9) and an inverted output (pin 6 or 8). I f the reset
input R (pin
or 13) is made L it is activated and the flip-flop i s forced t o the reset
output L and inverted output H. The
the flip-flop to the set state: output H and inverted output L.
If the set and reset inputs are both H, the condition of the clock input CL (pin 3 or 11) and
the data input D (pin 2 or 12) are important.
The logic level on the data input ( L or H) i s clocked into the flip-flop if the clock goes L to
H
now the output also becomes L or H.
6
or 7). I f the reset input R (pin 15 or 14) i s made L, it i s activated and the
output (pin
flip-flop is forced t o the reset condition: output L and inverted output H.
S
The set input
(pin 4 or 10) i s active when L and forces the flip-flop to the set condition :
output is H and inverted output is L.
I f both the
and reset inputs are H, the condition of the clock input C (pin 1 or 131, the
set
J-input (pin 3 or 11) and the K-input (pin 2 or 12) are important.
If the clock input goes from H t o L, the following occurs:
I f J
L and K
L:
the output states remain unchanged.
=
=
K
I f J
H and
L:
the output becomes H and the inverting output
=
=
I f J
L and K
H:
the cutput becomes L and the inverting output H.
=
=
I f J
H and K
H:
the outputs switch to the opposite state.
=
=
V.
...
L.
two
flip-flops.
input S (pin 4 or 10) is active when L and forces
set
5 V .
of the other
state
state:
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