Front Panel Controls - Tektronix 2432 Service Manual

Theory of Operation-2432 Service
bytes to be given to the System µP on its PA
0
-PA
7
(port
A-bits 0 through 7) outputs. It then asserts WRTOHOST
(write to host) HI, clocking the FPINT (front-panel interrupt)
at the
a
output of U861 B HI.
Depending on what the System µP is doing, it may
either service the interrupt request immediately, or it may
wait for time to be available. When it responds to the inter-
rupt, it does a read of the Front Panel "register" at
address 6209h. The decoded FPREG signal from Trigger
Holdoff Decoder U781 (diagram 12) allows OR-gates
U862B and U862C to pass the WR or RD signals. For a
read, both input pins to U862B are LO, causing the output
of U862A to go LO. This enables buffer U751, placing the
data from the Front Panel µP on the System µP data bus
(FP0-FP7) and, at the same time, resets flip-flop U861 B.
Resetting U861 B removes the front-panel interrupt and
sets HOSTDNRD (host done reading) to U700 HI.
When the System µP needs to write to the Front Panel
µP, it writes data to address 6209h. This latches data from
the System µP data bus into register U742. The enable to
U742 is via U862C. The latch enable also resets the Q
output of flip-flop U861A LO via U862D to produce the
WRTOFP (write to front-panel) interrupt to U700. Latching
data into U7 42 immediately frees the System µP to
resume other tasks, since it doesn't have to wait for the
Front Panel µP to service the interrupt.
When U700 services the interrupt by the System µP, it
sets FPRD (front-panel reading) LO and enables the
latched data in register U7 42 onto the Front Panel data
bus. It then reads the data into its internal registers and
asserts FPDNRD (front-panel done reading). FPDNRD
going HI clocks the FPDNRD status bit from flip-flop
U861A pin 6 HI to signal the System µP that it is done
reading the byte and removes the WRTOFP interrupt
present on U861 A pin 5. Each data byte transfer from the
System µP to the Front Panel µP and vice versa is done
using the two handshake routines just described.
Trigger Status Indicators
The Front Panel Trigger Status Indicators provide visual
information regarding trigger slope and trigger status to
the user. Data written to LED Register U741 from the Sys-
tem µP turns on the LED that reflects the current trigger
status. A LO output from U741 turns on the associated
LED. The LED Register is enabled by a System µP write
to address 6208h. Trigger Holdoff Decoder U781 (diagram
12) produces the decoded LEDREG signal that enables
data at the input pins to be latched when the WR clock
goes HI.
3-30
FRONT PANEL CONTROLS
The Front Panel is the operator's interface for control-
ling the user-selectable oscilloscope functions.
All of the Front Panel controls (diagram 4) are "soft"
controls in that they are not connected directly into the
signal path. Therefore, associated circuits are not
influenced by the physical parameters (such as capaci-
tance, resistance, and inductance) of the controls. In addi-
tion, converting the analog output levels of the potentiom-
eters to digital equivalent values allows the System µP and
the Front Panel µP to handle the data in ways that
enhance control operation.
The variables defining the current settings of the control
pots and the front-panel switches are stored and continu-
ally updated in Nonvolatile RAM U664 (diagram 1) by the
System µP. The data remains stored when the oscillo-
scope is turned off so that when the scope is turned on
again the System µP returns to the same front-panel
setup that was present when the scope was turned off.
Front-Panel Switch Scanner
The Front Panel switches are arranged in an electrical
array of eight rows and six columns. Switches are placed
at row-column intersections, and when a switch is closed,
one of the row lines is connected to one of the column
lines through an isolation diode. Checking for switch condi-
tions (open or closed) is done by setting a single row line
LO and then sequentially checking the six columns to
determine if a LO is present on any of the column lines.
After each column line in a row is checked, the current
row line is reset HI and the next row line is set LO to
check the next six columns. A complete check of the
front-panel switches consists of setting all eight row lines
LO in order and performing a six-column scan for each
column to check for a LO.
A row is selected for checking by the Front Panel µP
(U700, diagram 3) when it switches the MUXSEL lines
(0-2) applied to multiplexer U903 to set a row line LO. To
check the columns, the processor pulses its S/L
(shift/load) select line to shift register U904 first LO and
then HI. This causes a parallel load of the six column-line
bits (plus the seventh and eighth bits tied HI by R934) into
the shift register. The processor then generates eight shift
clocks (SHCLK) to U904, serially shifting the switch data
out on the SWOUT (switch data out) line. The serial data
bits are applied to the PB0 input (pin 25) of the Front
Panel µP to be checked. Any LO bits in the column-line
data tell the µP that a switch is closed. Since the Front
Panel µP knows which row line it set LO, it can determine
from the position of the LO bits in the serial data string
which of the switches are closed.