Acquisition Process And Control; Data Clocking To - Tektronix 2432 Service Manual

Theory of Operation-2432 Service
At this point in the sampling process the Time Base
Controller is waiting for a triggering gate from the Trigger
System to complete the acquisition (see "Acquisition Pro-
cess and Control"). Extra pretrigger samples acquired
while waiting for a trigger will either be flushed out of the
output wells of the CCDs (FISO mode) or converted and
stored in the circular Acquisition Memory (diagram 8), but
riot moved to the Save Memory (Short-Pipeline mode). The
exception to this is ROLL mode; a trigger event is not
required for ROLL acquisitions. Digitized data is moved
through the Acquisition System to continually update the
display with each waveform data point acquired.
ACQUISITION PROCESS AND CONTROL
To do a waveform acquisition, the System µP
addresses the internal instruction registers within the Time
Base Controller and then writes the setup data into the
registers. The setup data defines the acquisition mode
(FISO, Short-Pipeline, or ROLL), the time base clocking
rate (for the SEC/DIV setting), the trigger position, and
other instructions for how an acquisition is to be made.
Once the setup data is in the Time Base Controller
instruction registers, the System µP generates a strobe
that starts the acquisition and turns control of the Acquisi-
tion System over to the Time Base Controller. The Time
Base Controller then begins monitoring the CCD Phase
Clocks to determine when an adequate number of analog
samples are in the CCDs to fill the pretrigger require-
ments. When those samples have been obtained, the Time
Base Controller enables the Trigger Logic Array
(diagram 11) to accept a trigger and begins looking for a
triggering gate from the Trigger Logic Array (via the CCD
Phase Clock Array). This waiting period is the continuous
analog sampling state for the CCDs referred to at the end
of the "Input Signal Conditioning and Analog Sampling"
discussion.
With the Trigger System enabled, the A/B Trigger Gen-
erator (diagram 11) monitors the selected source for a sig-
nal that meets the analog triggering criteria. Source selec-
tion and triggering criteria are controlled by serial data
writes from the System µP (via the Data MUX Select cir-
cuit) based on the Front Panel settings selected by the
user. When the analog triggering conditions are met, the
A/B Trigger Generator gates the Trigger Logic Array. Once
enabled, the Trigger Logic Array monitors other triggering
criteria (Trigger Mode, Delay Time setting, Hold Off timing,
etc.) to determine the actual "Record" trigger point in the
waveform data record. The System µP writes data control
bits defining the Trigger Logic Array operating mode to the
internal registers of the Trigger Logic Array via the
Acquisition Control Registers.
3-10
When the Trigger Logic Array determines that the addi-
tional triggering conditions are also met, the Time Base
Controller is gated (via the CCD Phase Clock Array), and
the post-trigger samples are taken (if required) to finish the
acquisition. How the acquisition is completed after the
trigger point is determined, depends on the analog sam-
pling mode in effect.
FISO Mode
For FISO mode, the CH 1 and CH 2 CCDs must each
hold 1024 samples (plus some extra samples used in
locating the correct trigger point). After the trigger event,
the Time Base Controller counts a sampling clock from the
CCD Phase Clock Generator to determine when enough
post-trigger samples have been shifted into the CCDs to
finish the acquisition. When the record is filled, the analog
sampling process is stopped by disabling the sampling
clocks output by the CCD Phase Clock Generator. Con-
verting the stored analog information into digital data and
saving it into the Acquisition Memory is then started. Both
the "conversion" and "save" aspects of the acquisition
process are discussed in "Analog Data Conditioning and
A/D
Conversion" and "Acquisition Processing and
Display."
Short-Pipeline Mode
For Short-Pipeline acquisitions, each CCD can contain
only 37 samples before the "pipe" is full. This means that
samples must be continuously shifted through the digitiz-
ing process and into Acquisition memory as the samples
are being taken. Since the pretrigger and post-trigger dis-
tribution of the data in the acquisition record is not defined
until a trigger occurs, converted data is continually stored
in the Acquisition Memory. If the Acquisition Memory
space should become filled before a trigger occurs, newly
acquired data will simply displace the old in a circular
manner (oldest data replaced first). After a trigger, the
Time Base Controller counts another sampling clock to
determine when enough samples have been moved into
the Acquisition Memory to satisfy the post-trigger require-
ments and then turns the Acquisition Memory space over
to the Waveform µP. The Waveform µP transfers the sam-
ples into the Save Memory for eventual display.
FISO Mode
DATA CLOCKING TO
ACQUISl1"1ON MEMORY
In FISO mode, the Time Base Controller signals the
CCD Phase Clock Array (U470, diagram 11) to begin
clocking waveform samples out of the CCDs. The Time
Base Controller monitors the Trigger Location signals from
the CCD Phase Clock Array to determine precisely where
in the acquisition the trigger occurred. When the samples