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Hardware Design Files
4.2 PCB Layout
Minimize the switching node rise and fall times for minimum switching loss. Proper layout of the components
minimizing high-frequency current path loop is important to prevent electrical and magnetic field radiation and
high-frequency resonant problems. This PCB layout priority list must be followed in the order presented for
proper layout:
1. Place the input capacitor as close as possible to the PMID pin and GND pin connections and use the
shortest copper trace connection or GND plane.
2. Place the inductor input terminal as close to the SW pin as possible. Minimize the copper area of this trace
to lower electrical and magnetic field radiation but make the trace wide enough to carry the charging current.
Do not use multiple layers in parallel for this connection. Minimize parasitic capacitance from this area to any
other trace or plane.
3. Put an output capacitor near to the inductor and the IC. Tie ground connections to the IC ground with a short
copper trace connection or GND plane.
4. Place decoupling capacitors next to the IC pins and make the trace connection as short as possible.
5. A critical point is that the exposed power pad on the backside of the IC package must be soldered to the
PCB ground. Make sure that there are sufficient thermal vias directly under the IC connecting to the ground
plane on the other layers.
6. The via size and number must be enough for a given current path.
7. For more layout guidelines and recommendations refer to the data sheet of the respective battery charger
IC.
8. See the EVM design for the recommended component placement with trace and via locations. For the QFN
information, refer to
Quad Flatpack No-Lead Logic Packages Application Report
Attachment Application
4.2.1 Board Layout
The board layout is shown in
Figure 4-2. Top Overlay
8
BQ25308 Evaluation Module
Report.
Figure 4-2
to
Figure
4-7.
Copyright © 2024 Texas Instruments Incorporated
and
QFN and SON PCB
Figure 4-3. Top Solder
SLUUD09 – APRIL 2024
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