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Fa Nene
TES
Pin from which TES signal is output to DSP.
"High Frequency Level" is used to judge whether the main beam position is on top of
:
bit or on top of mirror.
CLV error signal input pin from DSP.
Al
RFSM
RF output pin.
RF gain setting and EFM signal 3T compensation constant setting pin together with
RFSM pin.
RFS-
fe nN
OG
SLI
DGND
;
FSC
DS
Input pin which control the data slice level by the DSP.
Digital system GND.
,
iN nm
P.
Output pin to which external focus search smoothing capacitor is connected.
"Tracking Balance Control" EF balance variable range setting pin.
s
Disc defect detector output pin.
Reference clock input pin. 4.23 MHz of the DSP is input.
iw)
do
E)
CLK
fs oO
wn Qo
Microprocessor command clock input pin.
Microprocessor command data input pin.
Microprocessor command chip enable input pin.
ee
DAT
wa
MmiMmMint[
un Wm]
n
ela
nl_
wm
Be]
N
g
Lea
a a
a |i
R
SS
vcc2
a 7
< P|
LF2
PH1
H
DD
LDS
Vcc!
oO
a 3
R12
Cl]
a
53
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