Theory Of Operation - Analog Devices DC3205A Demo Manual

THEORY OF OPERATION

Introduction to the DC3205A
The DC3205A demonstration circuit features the
LTC3314A, 5V, dual 4A/dual-phase 8A step-down DC/
DC regulator. The LTC3314A contains two monolithic,
constant frequency, current mode step-down DC/DC
converters. An oscillator, shared by two converters, with
frequency set by a resistor on the RT pin, turns on the
internal top power switch at the beginning of each clock
cycle. The beginning of each clock cycle of the two con-
verters are 180-degree out of phase. Current in the induc-
tor then increases until the top switch comparator trips
and turns off the top power switch. The peak inductor
current, at which the top switch turns off, is controlled by
the voltage on the internal V
the error amplifier. When operating in dual-phase mode,
V of Buck1 is used to control the peak current for both
C
buck power stages. The internal V
with internal compensator to stabilize the control loop.
The error amplifier servos the V
voltage on the FB pin with an internal 500mV reference.
When the load current increases, it causes a reduction
in the feedback voltage relative to the reference leading
the error amplifier to raise the V
age inductor current matches the new load current. When
the top switch turns off, the synchronous bottom power
switch turns on until the next clock cycle begins. In pulse-
skipping mode and Burst mode, the bottom switch also
turns off when inductor current falls to zero. If overload
conditions result in excessive current flowing through
the bottom switch, the next clock cycle will be delayed
until the switch current returns to a safe level. In Burst
Mode, the error amplifier and most part of the internal
circuitry can be turned off until output voltage trips an
output low comparator, during extreme light load condi-
tion, to improve light load efficiency.
If the EN1 pin is low, the DC3205A is in shutdown and in
a low quiescent current state. When the EN1 pin is above
its threshold, the DC3205A will be enabled.
The MODE/SYNC pin synchronizes the switching fre-
quency to an external clock. It also sets the PWM mode.
The PWM modes of operation are Burst, pulse-skipping
node, which is the output of
C
node is connected
C
node by comparing the
C
voltage until the aver-
C
DEMO MANUAL DC3205A
and forced continuous. See the LTC3314A data sheet for
more detailed information.
The maximum allowable operating frequency is influenced
by the minimum on time of the top switch, the ratio of
V to V and the available inductor values. The maxi-
OUT IN
mum allowable operating frequency may be calculated in
the formula below.
V
OUT
f =
SW(MAX)
V • t
IN(MAX)
Select an operating switching frequency below f
Typically, it is desired to obtain an inductor current of 30%
of the maximum LTC3314A operating load, 4A. Use the
formulas below to calculate the inductor value to obtain
a 30% (1.2A) inductor ripple for the operating frequency.
⎛
V
OUT
L ≥
• 1–
⎜
1.2A • f V
⎝
SW
V
OUT
≤ 0.5
V
IN(MAX)
0.25 • V
IN(MAX)
L ≥
for
1.2A • f
SW
The overall control loop of the converter can be tuned
by output capacitors and a feedforward capacitor. The
LTC3314A has been designed to operate at a high
bandwidth for fast transient response capabilities. This
reduces required output capacitance to meet the desired
transient voltage range. Feedforward capacitor C19 along
with R3 provides a phase lead which will improve the
phase margin.
Loop stability is generally measured using the Bode Plot
method of plotting loop gain in dB and phase shift in
degrees. The 0dB crossover frequency should be less
the 1/6 of the operating frequency to reduce the effects
of added phase shift of the modulator. The control loop
phase margin goal should be 45° or greater and a gain
margin goal of 8dB or greater.
ON(MIN)
SW(MAX)
⎞
V
OUT
⎟ for
⎠
IN(MAX)
V
OUT
> 0.5
V
IN(MAX)
(2)
.
(3)
(4)
Rev. 0
5