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Circuit Diagrams and PWB Layouts
SSB: Channel Decoder DVB-T
2T01 A8
2T08 C9
2T14 C11
2T19 D8
2T25 B7
2T04 C8
2T09 C9
2T15 C12
2T20 E6
2T26 C3
2T05 C8
2T12 C11
2T16 C11
2T21 E6
2T27 B8
2T07 C8
2T13 C11
2T18 D7
2T24 F5
2T28 H5
1
2
3
CHANNEL DECODER DVB-T
B03B
A
B
IT11
9T20
RES
C
IT42
3T19
TUN-AGC
100K
RES
4
FT42
3T13
IT15
TUN-AGC-MON
BC847BPN
7T18-2
5
100K
3
3T16
IT26
1K0
D
AGC-COMP
RESET-SYSTE M
TDA-IF-AGC
E
4-MHz
F
SDA-SSB
SCL-SSB
G
IF-N
IF-P
H
3139 123 6427.1
1
2
3
Q522.3E LA
2T29 H5
2T36 C9
3T07 G8
3T11 E7
3T18 G8
3T26 F5
2T31 D2
3T01 H4
3T08 D7
3T13 C2
3T19 C2
3T28 F5
2T32 A8
3T02 H4
3T09 D7
3T14 C4
3T20 B7
3T29 G8
2T35 C8
3T06 D8
3T10 E7
3T16 D3
3T21 D3
3T30 G7
4
5
+3V3DVB
IT22
6
IT27
2
7T18-1
BC847BPN
1
2T24
FT41
100n
IT32
3T26
100R
3T28
100R
2T28
3T01
390R
10n
3T02
2T29
390R
10n
4
5
7.
55
3T31 H8
5T09 A7
7T18-2 C3
FT11 B8
FT41 F3
3T32 G13
7T17-1 E9
7T25 A8
FT15 A8
FT42 C2
3T33 G12
7T17-2 H10
9T03 G8
FT17 F8
IT03 B7
5T08 B8
7T18-1 D4
9T20 C2
FT40 F9
IT07 D9
6
7
8
+1V2-PNX8541
IT41
5T09
FT15
+1V2DVB
120R
RES
7T25
LD3985M122
1
5
IN
OUT
IT24
IT25
3T20
3
4
INH
BP
100K
COM
IT03
5T08
FT11
+3V3
+3V3DVB
120R
+5V-TUN
+5V-TUN
IT07
IT08
3T10
18K
3T11
10K
TDA10048HN
IT18
IT31
FT17
JTAG-TDO
3T18
+3V3DVB
10K
JTAG-TCK
JTAG-TDI
JTAG-TMS
JTAG-TRS T
IT45
6
7
8
IT08 E7
IT17 H12
IT25 A8
IT32 F6
IT43 E11
IT11 C3
IT18 F7
IT26 D3
IT33 H9
IT45 H9
IT15 C2
IT22 D3
IT27 D3
IT41 A7
IT16 G12
IT24 A7
IT31 F6
IT42 C2
9
10
11
7T17-1
42
AGC_IF
IT43
43
AGC_TUN
7
18
XIN
DEN
MAIN
FT40
8
32
XOUT
41
20
CLR
0
21
1
33
22
SADDR
2
23
3
35
DO
24
SCL
4
34
I2C ADDRESS 10
25
SDA
5
26
6
39
27
TCK
7
38
TDI
40
GPIO<0:3>
TDO
37
19
TMS
OCLK
36
TRST
17
PSYNC
2
M
3
VI
16
P
SCL
TUN
15
SDA
IT33
7T17-2
TDA10048HN
VIA
50
56
51
VIA
55
VIA
52
VIA
VIA
9
10
11
12
13
B03B
A
B
C
D
E
FE-VALID
AGC-COMP
FE-DATA0
FE-DATA1
F
FE-DATA2
FE-DATA3
FE-DATA4
FE-DATA5
FE-DATA6
FE-DATA7
FE-CLK
FE-SOP
+3V3DVB
G
IT16
SCL-TUNER
IT17
SDA-TUNER
H
I_18300_015.eps
290908
12
13
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