Rohm LAPIS ML610Q411-NNNTBZ03A7 Manuals

Manuals and User Guides for Rohm LAPIS ML610Q411-NNNTBZ03A7. We have 1 Rohm LAPIS ML610Q411-NNNTBZ03A7 manual available for free PDF download: User Manual

Rohm LAPIS ML610Q411-NNNTBZ03A7 User Manual (383 pages)

Brand: Rohm | Category: Microcontrollers | Size: 4 MB

Table of Contents
6
Overview
16
Features
17
Block Diagram of ML610Q411
21
Configuration of Functional Blocks
21
Block Diagram of ML610Q412
22
Pin Layout
23
Pins
23
Pin Layout of ML610Q411 Chip
25
Pin Layout of ML610Q412 Chip
26
Pad Coordinates of ML610Q411 Chip
27
Pad Coordinates of ML610Q412 Chip
28
List of Pins
29
Description of Pins
32
Termination of Unused Pins
36
CPU and Memory Space
37
Overview
38
Program Memory Space
38
Data Memory Space
39
Data Type
39
Instruction Length
39
Description of Registers
40
List of Registers
40
Data Segment Register (DSR)
41
Reset Function
42
Configuration
43
Features
43
List of Pin
43
Overview
43
Description of Registers
44
List of Registers
44
Reset Status Register (RSTAT)
44
Description of Operation
45
Operation of System Reset Mode
45
MCU Control Function
46
Configuration
47
Features
47
Overview
47
Description of Registers
48
List of Registers
48
Stop Code Acceptor (STPACP)
49
Standby Control Register (SBYCON)
50
Block Control Register 0(BLKCON0)
51
Block Control Register 1(BLKCON1)
52
Block Control Register 2(BLKCON2)
53
Block Control Register 3(BLKCON3)
54
Block Control Register 4(BLKCON4)
55
Description of Operation
57
HALT Mode
57
Program Run Mode
57
STOP Mode
58
STOP Mode When CPU Operates with Low-Speed Clock
58
STOP Mode When CPU Operates with High-Speed Clock
59
Note on Return Operation from STOP/HALT Mode
60
Block Control Function
61
Interrupts (Ints)
62
Features
63
Overview
63
Description of Registers
64
List of Registers
64
Interrupt Enable Register 1 (IE1)
65
Interrupt Enable Register 2 (IE2)
66
Interrupt Enable Register 3 (IE3)
67
Interrupt Enable Register 4 (IE4)
68
Interrupt Enable Register 5 (IE5)
69
Interrupt Enable Register 6 (IE6)
70
Interrupt Enable Register 7 (IE7)
71
Interrupt Request Register 0 (IRQ0)
72
Interrupt Request Register 1 (IRQ1)
73
Interrupt Request Register 2 (IRQ2)
74
Interrupt Request Register 3 (IRQ3)
75
Interrupt Request Register 4 (IRQ4)
76
Interrupt Request Register 5 (IRQ5)
77
Interrupt Request Register 6 (IRQ6)
78
Interrupt Request Register 7 (IRQ7)
79
Description of Operation
80
Maskable Interrupt Processing
81
Non-Maskable Interrupt Processing
81
Software Interrupt Processing
81
Notes on Interrupt Routine
82
Interrupt Disable State
85
Clock Generation Circuit
86
Configuration
87
Features
87
Overview
87
Description of Registers
88
Frequency Control Register 0 FCON0
88
Frequency Control Register 1 FCON1
88
List of Pins
88
List of Registers
88
Description of Operation
92
Low-Speed Clock
92
Low-Speed Clock Generation Circuit
92
Operation of Low-Speed Clock Generation Circuit
93
500 Khz RC Oscillation
94
High-Speed Clock
94
External Clock Input Mode
95
Operation of High-Speed Clock Generation Circuit
96
Switching of System Clock
98
Functioning P21 (OUTCLK) as the High Speed Clock Output
100
Specifying Port Registers
100
Functioning P22 (LSCLK) as the Low Speed Clock Output
101
Time Base Counter
102
Configuration
103
Features
103
Overview
103
Description of Registers
105
List of Registers
105
Low-Speed Time Base Counter (LTBR)
106
High-Speed Time Base Counter Divide Register (HTBDR)
107
Low-Speed Time Base Counter Frequency Adjustment Registers L and H (LTBADJL, LTBADJH)
108
Description of Operation
109
Low-Speed Time Base Counter
109
High-Speed Time Base Counter
110
Low-Speed Time Base Counter Frequency Adjustment Function
111
A Signal Generation for 16Bit Timer 2-3 Frequency Measurement Mode
112
Capture
113
Configuration
114
Features
114
List of Pins
114
Overview
114
Description of Registers
115
List of Registers
115
Capture Control Register (CAPCON)
116
Capture Status Register (CAPSTAT)
117
Capture Data Register 0 (CAPR0)
118
Capture Data Register 1 (CAPR1)
119
Description of Operation
120
Khz Timer (1Khztm)
121
Configuration
122
Features
122
Overview
122
Description of Registers
123
List of Registers
123
Khz Timer Count Registers (T1KCRL, T1KCRH)
124
Khz Timer Control Register (T1KCON)
125
Description of Operation
126
Timers
127
Configuration
128
Features
128
Overview
128
Timer 0 Data Register (TM0D)
131
Timer 1 Data Register (TM1D)
132
Timer 2 Data Register (TM2D)
133
Timer 3 Data Register (TM3D)
134
Timer 0 Counter Register (TM0C)
135
Timer 1 Counter Register (TM1C)
136
Timer 2 Counter Register (TM2C)
137
Timer 3 Counter Register (TM3C)
138
Timer 0 Control Register 0 (TM0CON0)
139
Timer 1 Control Register 0 (TM1CON0)
140
Timer 2 Control Register 0 (TM2CON0)
141
Timer 3 Control Register 0 (TM3CON0)
142
Timer 0 Control Register 1 (TM0CON1)
143
Timer 1 Control Register 1 (TM1CON1)
144
Timer 2 Control Register 1 (TM2CON1)
145
Timer 3 Control Register 1 (TM3CON1)
146
Description of Operation
147
Timer Mode Operation
147
16-Bit Timer Frequency Measurement Mode Operation
148
16-Bit Timer Frequency Measurement Mode Application for Setting Uart Baud-Rate
150
Pwm
151
Configuration
152
Features
152
Overview
152
Description of Registers
153
List of Pins
153
List of Registers
153
PWM0 Period Registers (PW0PL, PW0PH)
154
PWM0 Duty Registers (PW0DL, PW0DH)
155
PWM0 Counter Registers (PW0CH, PW0CL)
156
PWM0 Control Register 0 (PW0CON0)
157
PWM0 Control Register 1 (PW0CON1)
158
Description of Operation
159
Functioning P43 (PWM0) as the PWM Output
161
Specifying Port Registers
161
Functioning P34 (PWM0) as the PWM Output
162
Watchdog Timer
163
Configuration
164
Features
164
Overview
164
Description of Registers
165
List of Registers
165
Watchdog Timer Control Register (WDTCON)
166
Watchdog Timer Mode Register (WDTMOD)
167
Description of Operation
168
Synchronous Serial Port
170
Configuration
171
Features
171
Overview
171
List of Pins
172
List of Registers
173
Serial Port Transmit/Receive Buffers (SIO0BUFL, SIO0BUFH)
174
Serial Port Control Register (SIO0CON)
175
Serial Port Mode Register 0 (SIO0MOD0)
176
Serial Port Mode Register 1 (SIO0MOD1)
177
Description of Operation
178
Transmit Operation
178
Receive Operation
179
Transmit/Receive Operation
180
Functioning P42 (SOUT0), P41 (SCK0) and P40 (SIN0) as the SSIO/ "Master Mode
181
Specifying Port Registers
181
Functioning P42 (SOUT0), P41 (SCK0) and P40 (SIN0) as the SSIO/ "Slave Mode
182
Functioning P46 (SOUT0), P45 (SCK0) and P44 (SIN0) as the SSIO/ "Master Mode
183
Functioning P46 (SOUT0), P45 (SCK0) and P44 (SIN0) as the SSIO/ "Slave Mode
184
Uart
185
Configuration
186
Features
186
List of Pins
186
Overview
186
Description of Registers
187
List of Registers
187
UART0 Transmit/Receive Buffer (UA0BUF)
188
UART0 Control Register (UA0CON)
189
UART0 Mode Register 0 (UA0MOD0)
190
UART0 Mode Register 1 (UA0MOD1)
191
UART0 Baud Rate Registers L, H (UA0BRTL, UA0BRTH)
193
UART0 Status Register (UA0STAT)
194
Description of Operation
196
Transfer Data Format
196
Baud Rate
197
Transmit Data Direction
198
Transmit Operation
199
Receive Operation
201
Functioning P43(TXD0) and P42(RXD0) as the UART
203
Specifying Port Registers
203
Functioning P43(TXD0) and P02(RXD0) as the UART
204
I 2 C Bus Interface
206
Configuration
207
Features
207
List of Pins
207
Overview
207
Description of Registers
208
List of Registers
208
I 2 C Bus 0 Receive Register (I2C0RD)
209
I 2 C Bus 0 Slave Address Register (I2C0SA)
210
I 2 C Bus 0 Transmit Data Register (I2C0TD)
211
I 2 C Bus 0 Control Register (I2C0CON)
212
I 2 C Bus 0 Mode Register (I2C0MOD)
213
I 2 C Bus 0 Status Register (I2C0STAT)
214
Communication Operating Mode
215
Control Register Setting Wait State
215
Data Receive Mode
215
Data Transmit Mode
215
Description of Operation
215
Slave Address Transmit Mode
215
Start Condition
215
Stop Condition
216
Communication Operation Timing
217
Operation Waveforms
219
Functioning P41(SCL) and P40(SDA) as the I2C
220
Specifying Port Registers
220
NMI Pin
221
Configuration
222
Features
222
List of Pins
222
Overview
222
Description of Registers
223
List of Registers
223
NMI Data Register (NMID)
224
NMI Control Register (NMICON)
225
Description of Operation
226
Interrupt Request
226
Port 0
227
Configuration
228
Features
228
List of Pins
228
Overview
228
Description of Registers
229
List of Registers
229
Port 0 Data Register (P0D)
230
Port 0 Control Registers 0, 1 (P0CON0, P0CON1)
231
External Interrupt Control Registers 0, 1 (EXICON0, EXICON1)
232
External Interrupt Control Register 2 (EXICON2)
233
Description of Operation
234
External Interrupt/Capture Function
234
Interrupt Request
234
Configuration
237
Features
237
List of Pins
237
Overview
237
Description of Registers
238
List of Registers
238
Port 1 Data Register (P1D)
239
Port 1 Control Registers 0, 1 (P1CON0, P1CON1)
240
Description of Operation
241
Input Port Function
241
Secondary Function
241
Configuration
243
Features
243
List of Pins
243
Overview
243
Port2
243
Description of Registers
244
List of Registers
244
Port 2 Data Register (P2D)
245
Port 2 Control Registers 0, 1 (P2CON0, P2CON1)
246
Port 2 Mode Register (P2MOD)
247
Description of Operation
248
Output Port Function
248
Secondary Function
248
Configuration
250
Features
250
Overview
250
List of Pins
251
Description of Registers
252
List of Registers
252
Port 3 Data Register (P3D)
253
Port 3 Direction Register (P3DIR)
254
Port 3 Control Registers 0, 1 (P3CON0, P3CON1)
255
Port 3 Mode Registers 0, 1 (P3MOD0, P3MOD1)
257
Description of Operation
259
Input/Output Port Functions
259
Secondary and Tertiary Functions
259
Configuration
261
Features
261
Overview
261
List of Pins
262
Description of Registers
263
List of Registers
263
Port 4 Control Registers 0, 1 (P4CON0, P4CON1)
266
Port 4 Mode Registers 0, 1 (P4MOD0, P4MOD1)
268
Description of Operation
271
Input/Output Port Functions
271
Secondary and Tertiary Functions
271
Port a
272
Configuration
273
Features
273
List of Pins
273
Overview
273
Description of Registers
274
List of Registers
274
Port a Data Register (PAD)
275
Port a Direction Register (PADIR)
276
Port a Control Registers 0, 1 (PACON0, PACON1)
277
Description of Operation
279
Input/Output Port Functions
279
Buzzer
280
Configuration
281
Features
281
List of Pins
281
Overview
281
Description of Registers
282
List of Registers
282
Buzzer 0 Control Register (MD0CON)
283
Buzzer 0 Tempo Code Register (MD0TMP)
284
Buzzer 0 Scale Code Register (MD0TON)
285
Buzzer 0 Tone Length Code Register (MD0LEN)
286
Description of Operation
287
Operations of Buzzer Output
287
Functioning P22 (MD0) as the Buzzer Output
288
Specifying Port Registers
288
RC Oscillation Type A/D Converter
289
Configuration
290
Features
290
Overview
290
List of Pins
291
Description of Registers
292
List of Registers
292
RC-ADC Counter a Registers (RADCA0-2)
293
RC-ADC Counter B Registers (RADCB0-2)
294
RC-ADC Mode Register (RADMOD)
295
RC-ADC Control Register (RADCON)
296
Description of Operation
297
RC Oscillator Circuits
297
Counter A/Counter B Reference Modes
303
Example of Use of RC Oscillation Type A/D Converter
304
Monitoring RC Oscillation
309
Functioning P35(RCM), P34(RCT0), P33(RT0), P32(RS0), P31(CS0) and P30(IN0) as the RC-ADC(Ch0)
310
Specifying Port Registers
310
Functioning P47(RT1), P46(RS1), P45(CS1) and P44(IN1) as the RC-ADC(Ch1)
311
Successive Approximation Type A/D Converter
312
Configuration
313
Features
313
Overview
313
List of Pins
314
Description of Registers
315
List of Registers
315
SA-ADC Result Register 0H (SADR0H)
316
SA-ADC Result Register 0L (SADR0L)
316
SA-ADC Result Register 1H (SADR1H)
317
SA-ADC Result Register 1L (SADR1L)
317
SA-ADC Control Register 0 (SADCON0)
318
SA-ADC Control Register 1 (SADCON1)
319
SA-ADC Mode Register 0 (SADMOD0)
320
Description of Operation
321
Settings of A/D Conversion Channels
321
Operation of the Successive Approximation A/D Converter
322
LCD Drivers
323
Features
324
Overview
324
Configuration of the LCD Drivers
325
Configuration of the Bias Generation Circuit
326
List of Pins
327
Description of Registers
329
List of Registers
329
Bias Circuit Control Register 0 (BIASCON)
330
Display Control Register (DSPCNT)
331
Display Mode Register 0 (DSPMOD0)
332
Display Control Register (DSPCON)
333
Display Registers (DSPR00 to DSPR23 or DSPR00 to DSPR2B)
334
Description of Operation
336
Operation of LCD Drivers and Bias Generation Circuit
336
Common Output Waveforms
338
Segment Output Waveform
339
Battery Level Detector
340
Configuration
341
Features
341
Overview
341
Description of Registers
342
List of Registers
342
Battery Level Detector Control Register 0 (BLDCON0)
343
Battery Level Detector Control Register 1 (BLDCON1)
344
Description of Operation
345
Threshold Voltage
345
Operation of Battery Level Detector
346
Power Supply Circuit
347
Configuration
348
Features
348
Overview
348
List of Pins
349
Description of Operation
350
On-Chip Debug Function
351
Method of Connecting to On-Chip Debug Emulator
352
Overview
352
Flash Memory Rewrite Function
353
Appendixes
354
Appendix A Registers

355
Appendix B Package Dimensions

359
Appendix C Electrical Characteristics

361
Appendix D Application Circuit Example

376
Appendix E Check List

377
- Revision History
  381

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Rohm LAPIS ML610Q411-NNNTBZ03A7 Manuals

Rohm LAPIS ML610Q411-NNNTBZ03A7 User Manual (383 pages)

Table of Contents

Appendix A Registers

Appendix B Package Dimensions

Appendix C Electrical Characteristics

Appendix D Application Circuit Example

Appendix E Check List

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