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OP
Reg
Core Storage
ITDI
P
I
Q
I
~
~~-----------------+~
Figure 64.
E Cycle of Transmit Digit Operation
Output Data Flow
Figure 66 shows how
MAR
causes the address of the
first character to be routed through
MBR
and
MDR
to
the output device. Succeedingly higher-numbered
Input Device
Disk Storage Drive
1620
Typewriter
Paper Tape Reader
Card Reader
positions in core storage follow until a record mark or
the 80th buffer storage position of the output card
is reached.
1620 Data Flow
The data
How
diagram shown in Figure 67 is used by
Customer Engineers for diagnostic analysis of the
1620. As shown in the upper section of the diagram,
core storage is addressed by
MAR.
Two digits, the
addressed digit and its adjacent position, read out of
core storage into the
MBR-E
and
MBR-O
registers. The
addressed digit is transferred to
MDR
for processing.
Both digits read back into core storage.
MAR
receives core storage addresses from the
twelve
MARS
registers .. The function of each
MARS
register is given in Appendix C.
Internal Checking
The 1620 is a self-checking unit. As shown in Figure
67 (lower left corner), both input and output data
are parity checked in the translators. Also, internal
parity chE:cking of data occurs in the
MBR-E,MBR-O,
and
MAR
registers.
Program Control
The Op register and decoding block are shown in the
lower right corner of Figure 67. Program execution
control lines, which result from decoding the instruc-
tion Op code, are initiated throughout the system as
required.
Core Storage
Contact Sense
ADC Register
1710
Manual Entry Switches
Real-Time Clock
TAS Register
Address of First Digit
Figure 65. Data Flow of Input Operation
Output Dev..ice
Disk Storage Drive
Typewriter
Paper T ape Punch
Card Punch
Plotter
Printer
Figure 66.
Data Flow of Output Operation
74
Core Storage

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