Infineon PSoC 61 Reference Manual page 426

PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture
Serial Communications Block (SCB)
– TX FIFO underflow – Hardware attempts to read from an empty TX FIFO.
2
• I C RX
– RX FIFO has more entries than the value specified by TRIGGER_LEVEL in SCB_RX_FIFO_CTRL.
– RX FIFO is full – The RX FIFO is full.
– RX FIFO is not empty – At least one data element is available in the RX FIFO to be read.
– RX FIFO overflow – Hardware attempts to write to a full RX FIFO.
– RX FIFO underflow – Firmware attempts to read from an empty RX FIFO.
2
• I C externally clocked
– Wake up request on address match – Active on incoming slave request (with address match). Only set when
EC_AM is '1'.
2
– I C STOP detection at the end of each transfer – Only set for a slave request with an address match, in EZ
and CMD_RESP modes, when EC_OP is '1'.
2
– I C STOP detection at the end of a write transfer – Activated at the end of a write transfer (I
event is an indication that a buffer memory location has been written to. For EZ mode, a transfer that only
writes the base address does not activate this event. Only set for a slave request with an address match, in
EZ and CMD_RESP modes, when EC_OP is '1'.
2
– I C STOP detection at the end of a read transfer – Activated at the end of a read transfer (I
event is an indication that a buffer memory location has been read from. Only set for a slave request with
an address match, in EZ and CMD_RESP modes, when EC_OP is '1'.
For more information on how to implement and clear interrupts see the I
PDL.
Reference manual
2
C (SCB_I2C_PDL) datasheet and the
426
2
C STOP). This
2
C STOP). This
002-27293 Rev. *E
2023-09-06