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4-37
Data/Status Multiplexers
4-38
These circuits determine the source of the data sup¬
plied to the Data Shifter. When the 6034A is not a talker and
RECEIVE HANDSHAKE is true {TALK A RECEIVE* HAND¬
SHAKE), the Data byte Multiplexer is enabled. DIO bits 1
through 7 from the HP-IB are then transferred to the Data
Shifter. The first bit in the data byte is the complement of the
data byte enable. When the enable is active (low) the first bit
in the data byte will be high. The first bit identifies the data be¬
ing supplied to the microprocessor via CRUIN as either a data
byte or a status byte, with bit 1 high signifying data byte.
4-39
The complement of the data byte enable aiso enables
the Status Byte Multiplexer. Therefore, when one multiplexer
is enabled the other is disabled. The status byte contains
seven bits that provide information about changes on the
HP 18 and the present state of the HP-IB. The first bit of the
status byte is tied low, signifying to the microprocessor a
status byte.
4-40
Data Shiftsr/Gutput Buffer
4-41
This circuit has an eight-bit parallel input and an
eight-bit parallel output. It also has a serial input and serial out¬
put. LOAD/SHIFT determines whether data is parallel loaded
in or serially shifted in and out. The loading or shifting occurs
upon receipt of pulses from isolator 12. Figure 4-2 shows data
flow through the Data Shifter in three cases.
4-42
In Figure 4-2A, DIO bits 1 through 7 are loaded from
the Data Byte Multiplexer into the data shifter by a T2 pulse
when LOAD/SHIFT is in LOAD state. After LOAD/SHTFT
changes to SHIFT state, T2 pulses shift data out of the data
shifter to CRUIN. In Figure 4-2B, data indicating the HP-IB
status is parallel loaded into the data shifter. Note that one of
the bits, the first one to be loaded into CRUIN, is hardwired
low. This identifies the data as a status byte. Figure 4-2C
shows data being serially loaded into the data shifter from the
microprocessor. The data outputs are enabled when the
6034A is enabled to talk or is serial polled.
4-43
Output bits 7 and 8 from the data shifter are con¬
nected to the DIO bus through 3-state buffers. When the
6034A is addressed as a talker, DIO 7 is driven by the data
shifter/output buffer. However, when the 6034A is serial poll¬
ed the DIO 7 data shifter output is disabled and DIO 7 is driven
directly by CHI to indicate whether the 6034A was requesting
service when it was polled. (DIO 7 is the only DIO line that can
be driven by CHI.) DIO 8 is driven by the data shifter only dur¬
ing serial poll. When the 6034A is addressed as a talker and is
sending data, the DIO 8 output is held high. However, thebit 8
output from the data shifter drives EOI on the HP-IB; EOI in¬
dicates last byte.
4-44
Isolation Components
4-45
The HP-IB circuits are isolated from the rest of the
6034A. This allows a system to be configured without a com¬
mon ground reference. Isolation also reduces the possibility of
forming ground loops in complex systems. Potential differences
between different grounds can iead to noise problems that are
difficult to locate and solve. In the 6034A both optical couplers
and transformers are used for isolation to maximize speed and
reliability.
4-46
MICROCOMPUTER
4-47
Figure 4-3 is a block diagram of the microcomputer
section of the 6034A, including the three DACs that program
output voltage, output current, and overvoltage protection.
The heart of the microcomputer is the Microprocessor.
Because many of the signals to and from the Microprocessor
are widely distributed, mnemonics are used in lieu of individual
connections to each block. The A9 through A13 and CRUCLK
outputs from the microprocessor are buffered for use in some
circuits. The buffered signals are identified by a prime symbol
(e.g., A9'). Note that the A13 output is also used for
CRUOUT, and is identified as A13 (or A13') wherever it is used
for addressing, and CRUOUT (or CRUOUT') wherever it sup¬
plies the CRUOUT signal from the microprocessor.
4-48
Memory Circuits
4-49
The ROM circuit consists of either one 64K masked
ROM or four 16K EPROMs. Factory-set jumpers in the
Memory Address Decoding circuits ensure the microprocessor
accesses the proper address in ROM. The block diagram is
based on 64K ROM, so ROM2, ROM3, and ROM4
are
not
used. Appendix C shows connections used for 16K EPROMs.
4-50
The RAM circuit consists of either two 256-bit RAMs
or two IK RAMs. Factory-set jumpers decode the RAMI,
WRITE ENABLE, and address inputs for the device in use.
4-51
Microprocessor interrupts
4-52
While the power supply is operating normally, with
no faults and no commands to implement, the microprocessor
program operates in an idle loop. When the microprocessor is
required to perform a task an interrupt must be generated. As
will be explained, this will occur at least every millisecond. The
6034A organizes interrupts into five priority levels, with a high
priority interrupt able to interrupt any lower level.
4-53
The highest priority interrupt is PON (Power ON).
Although not shown on the block diagram, the bias power
supplies for the HP-IB circuits and the microcomputer circuits
each produce a PON signal (PON1 and PON2) whenever the
unregulated dc input to the bias supplies is insufficient to en¬
sure proper output from the bias supplies to operate the digital
circuits. Normally this occurs only during power up or down,
or during brownout conditions. The PON circuits are designed
to ensure that during power up and down the PON signal will
exist while the digital circuits are able to operate, so that the
microcomputer will be interrupted, note the PON signal, and
be able to respond to a serial poll that PON has occurred.
4 5
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