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J-K Rip-Flop.
J-K flip-flops have two conditioning inputs, J
and K, which determine the state the flip-flop assumes upon
receipt of a positive-going clock pulse, C. In Figure B-17 the
J input is active high and the K input is active low.
Figure B-17.
Dual J-K Flip-Flop
Shift Register,
Figure B-18 shows a four-bit shift register. In
mode 1, data is parallel loaded into the four registers (pins
3,4,5,6) when the C input is low. In mode 2, data is serial load¬
ed into the first register (pin 2) when the C input is low. Note
that the C input also shifts data from the first register to the
second, etc. when in mode 2 (2-* indicates that the shift func¬
tion is dependent on mode 2). When enable is inactive (high),
3-state outputs are high impedance, but sequential operation
of the registers and the output at pin II (cascade output) are
not affected.
Binary Counter.Figure B-19 shows a four-bit binary counter
consisting of a divide-by-two section and a divide-by-eight sec¬
tion. When both inputs to the control block are active, the con¬
tent of both sections equals zero. If the output of the divide-
by-two section is connected to the input of the divide-by-eight
section, the device operates as a divide-by-16 counter.
!
1820-1446 T.I.SN74LS395N
Vcc pin 16
Gnd pin 8
JL*
R
SRG4
7
Ml (LOAD)
Lb,
JO*
M2 (SHIFT)
>C3/2—►
_3
2,30
1,3D
0
7
J5_
_4
1.3D
0
v
J4_
—5. 1,30
0
V
J3_
_6,
1,30
0
V
1!_
A4U40
A4U41
Figure B-18.
Shift Register
Figure B-19.
Binary Counter
B-10
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