Block (3 Of 8) Diagram - Panasonic TH-103VX200W Service Manual

TH-103VX200W

11.6. Block (3 of 8) Diagram

A DIGITAL SIGNAL PROCESSOR
IC8201 FPGA1
RESET
23
3D FORMAT
+2.5V +1.2V
20MHz +3.3V
IC8203 IC8204
A+3.3V
+2.5V +1.2V
A+1.8V
G
G
FL002
24
25
PI1D(0)-(29) 30bit
26
PI1HS,PI1VS
27
IC8202
CLOCK GEN
28 20MHz
29 28.6363MHz
74.25MHz
IC8206
+1.8V +1.8V
+3.3V
A+1.2V_M
20MHz
SUB+3.3V
FL4003
30
STB+5V
30
SUB+5V
31
STB+5V
P_ON/OFF
32
A+9V
DS_SOS
33
A+5V
IIC_INT
34
SUB+3.3V IC4009
35
5VRXD_TU
36
TXD_PC_M
37
A_RXD_PC
38
39
STB+3.3V IC4013
SUB+5V
40
5V 5V<-3.3V
41
5VTXD_TU
5VNRST
LED_G Q4008
REMOTE_IN
IIC_CONT
DPMS_VD_SCX1
DPMS_HD_SCX1
UART_SW
SOUND_MUTE
XIRQ3
KEY_INPUT
INFO_GENX3
LAN3V_ON/OFF
15V_ON/OFF
SLOT1_DET
RXD_LAN
TXD_LAN
DN_IIC_SW
DN_SOS
FAN_CONT
FAN_ON/OFF
FAN_SOS
PI2D(0)-(29)
30bit
+1.8V
IC4010
SCX IN B
SCX1(MASTER)
PI2D(0)-(9) IP CONVERTER
PI2D(10)-(19)
IC4011
PI2D(20)-(29)
HS,VS,CLK DDR_SDRAM
DDR_SDRAM
INTERFACE
SCX IN A
PI1D(0)-(9)
IC4012
PI1D(10)-(19)
PI1D(20)-(29) DDR_SDRAM
DDR_SDRAM
HS,VS,CLK INTERFACE
CLOCK IN
POCLK/74.25M
SCX1 IN
SCX1 IN
LVDS OUT
ROUT
SCX1(MASTER) GOUT
FL4004
BOUT
VIDEO SIGNAL PROCESSOR
G
+1.2V
G OSD
VSYNC
10bit LVDS
HSYNC
CLK_O
G
+3.3V SCX1(MASTER)
G
MICOM
DATA RST
FPGA_DATAIN
FLASH MEMORY
CLD
ASIC-ARM
FPGA_LD
INTER FACE IC4006
CLK
FPGA_CLK
ADDRESS
POWER_ON/OFF DATA
32Mbit
DS BOARD SOS (LED:10TIME) (LED:10TIME)
FLASH MEMORY
IIC_INT
3.3VRXD_TU
RXD_TU
TXD_TU
M_FPGA_CONFIG
RXD_PC
FPGA_DATA
FPGA_DATA
TXD_PC FPGA_DCLK
FPGA_DCLK
NSTATUS
NSTATUB
CONF_DONE
CONF_DONE
NCONFIG
NCONFIG
LSI_RESET3
Q4014
DRVMUTE
LED_G
PANEL SOS
REMOTE IN
PANEL_STBY_ON
IIC CONT
PANEL_STATUS
DPMS_HD
EEPROM_WP
DPMS_VD A+5V
A+5V SOS
UART_SW
(LED:13TIME) (LED:13TIME)
SOUND_MUTE
A+15V SOS
(LED:2TIME) (LED:2TIME)
XIRQ3
A SOS
Q2307
(LED:13TIME) (LED:13TIME)
KEY_INPUT
INFO_GENX3
36MHz
LAN3V_ON/OFF
IIC2
15V_ON/OFF SDA2/SCL2
IIC3
SLOT1_DET SDA3/SCL3
IIC4
RXD_LAN SDA4/SCL4
TXD_LAN SDA1/SCL1 IIC1
DN_IIC_SW
DN_SOS (LED:14TIMES) (LED:14TIMES)
MIHO_STB
MIHO_STB
FAN_CONT
MIHO_XIRQ
MIHO_XIRQ
FAN_ON/OFF
FAN_SOS (LED:11TIMES) (LED:11TIMES) UX_G101
UX_G101
FL4501
+1.8V
SCX IN B
PI1D(0)-(9)
PI1D(10)-(19)
PI1D(20)-(29)
HS,VS,CLK
CLOCK IN
POCLK/74.25M
SCX1 IN
A+1.2V_S
SCX1 IN
FL4503
G
+1.2V
G
SUB+3.3V
FL4502
SCX1(SLAVE)
G
VIDEO SIGNAL PROCESSOR
+3.3V
G
10bit LVDS
-
LVDS DATA(RIGHT)
+
RST
SUB+3.3V
FLASH MEMORY
A0-A20
ADDRESS
INTER FACE
DQ0-DQ15 DATA
IC4007
RESET
DISPEN
IC4004
ALARM
PANEL_STBY_ON
EEPROM
READY
A+15V
A+15V SOS ANALOG ASIC
Q2306,08
IC4802
STB3.3V REG
A+1.8V
STB_RESET
D2305 +1.8V SOS
STB5V
Q2303
A+3.3V
D2306 +9V SOS
STB+3.3V
Q2304
A+9V
+3.3V SOS
D2307
Q2305
STB_RST
SEL=L
A+1.8V A+3.3V A+5V A+9V
IIC1
D2308 D2310 D2312 D2314
SEL=H
D2315
D2309 D2311 D2313
A1.2V_M
SUB1.2V_M_SOS D2342
Q2319
A1.2V_S
SUB1.2V_S_SOS D2340
Q2317
SUB3.3V
SUB3.3V_SOS
D2341
Q2318
64
IC4501
IC4502
SCX1(SLAVE)
DDR_SDRAM
IP CONVERTER
DDR_SDRAM
INTERFACE
IC4503
DDR_SDRAM
INTERFACE DDR_SDRAM
TXD_PC_SD
A_RXD_PC
IIC_INT
LVDS OUT
ROUT
GOUT
-
LVDS DATA(LEFT)
BOUT
+
VSYNC
HSYNC
CLK_O
SCX1(SLAVE)
MICOM
LSI_RESET1
LSI_RESET1
LSI_RESET2
LSI_RESET2
LSI_RESET3
LSI_RESET3
HDMI_DET
HDMI_DET
36MHz
LVDS DATA(RIGHT)
IC4801 POWER/LED/REMOCON
CONTROL
GenX8
EEPROM_IIC
EEPROM_WP_G8
IIC_INT
IIC_INT
INFO_GENX3
INFO_GENX3
STB3.3V LED_G_G8
LED_G_G8
STB3.3V LED_R
LED_R
DPMS_HD
DPMS_HD
NRST DISPEN
DPMS_VD
DPMS_VD
PANEL_STBY_ON
EEPROM_IIC F15V_MON
(LED (LED 2TIMES) 2TIMES) F15V_MON
READY
REMOTE_IN
IIC REMOTE_IN
ALARM
STB_ON
IIC_SEL
STB_ON
IIC_SEL ALL_OFF
HIGH SCX1 ALL_OFF
LOW OPEN TXD_PC_GB
TXD_PC_GB
RXD_PC_GB
Q2320
RXD_PC_GB
SUB SOS
UART_SW1
UART_SW1
IIC_SW
10MHz
IIC_SW D_RXD
D_TXD
FOR
A4
FACTORY
USE
4 IIC_DATA1
3V_IIC1
5 IIC_CLK1
6 IIC_DATA2
P3V_IIC2
7 IIC_CLK2
8 IIC_DATA3
3V_IIC3
9 IIC_CLK3
10 TXD_PC_SD
11 A_RXD_PC
12 IIC_INT
A10 DN10
53
LVDS DATA(LEFT)
29
27
LVDS DATA(RIGHT)
3
A16
DN16
FPGA_DATA
29
FPGA_DCLK
27
NSTATUS
25
CONF_DONE
24
NCONFIG
23
FPGA1_NCEO
22
20
P3V_IIC3
18
LSI_RESET3
16
DN_IIC_SW
14
DN_SOS
13
MIHO_STB
12
MIHO_XIRQ
9
3D_LED_L
7
UX_G101
6
A3
D3
1
DRVMUTE
2 PANEL STBY_ON
3 PANEL STATUS
4 PANEL SOS
7 IIC_DATA1
3V_IIC4
8 IIC_CLK1
10 IIC_DATA2
D_IIC2
11 IIC_CLK2
D_RXD
13
14 D_TXD