Table of Contents
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Principles of Operation
Read-Only Memory (ROM)
The INP has a 4K word, high-speed NMOS ROM. The ROM contains power-on and reset programs,
functional diagnostics, loader/dumper routines, and RAM fault location code.
Random Access Memory (RAM)
The INP has 24K words of static RAM that store the protocol driver in use (such as BISYNC
point-to-point), the INP's control program, the HP 3000 interface driver, and data buffers for the
communication channel.
Memory-protect circuitry and separate power supply lines are provided for the RAM and other associated
support circuitry to assure that no data will be lost in the event of a power failure or "brownout".
Direct Memory Access (DMA)
The INP uses an LSI DMA -controller chip to provide three high -speed channels between data buffers in
RAM and the HP-IB Interface, as well as between RAM and datacomm LSI devices. The function of the
DMA logic is to move bytes between external devices and RAM in such a way that they will be
transparent to the INP Microprocessor software. This ability to transfer data concurrently with
instruction execution enables the INP to achieve high throughput rates.
SOLC and BISYNC Data Communication
The INP uses LSI datacomm devices that are programmed by the INP Microprocessor to operate with
BISYNC and SDLC protocols. When transmitting, these devices receive data and control bytes in parallel
from the INP Microprocessor and convert them into a continuous serial stream for transmission.
Simultaneously, they can receive a serial stream of data and control information and assemble it into a
series of parallel data bytes for the INP Microprocessor.
Communication Line Interfaces
The communication line interfaces, such as RS-232-C, Bell DDS, Direct-connect, etc., translate data and
control lines into signals that are electrically and mechanically compatible with the respective standards.
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Troubleshooting
