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Principles of Operation
3-2. INP Microprocessor
The Complementary-Metal-Oxide-Semiconductor/Silicon-on-Sapphire
(CMOS/SOS) Microprocessor is the heart of the !NP.
It is a
high~
performance, low-power-consumption microprocessor primarily
used
in
controller applications.
It offers a one-microsecond typical
instruction cycle time to execute any of the fixed-width,
16-bit
instructions.
These
instructions
can
process
one-,
four-,
eight-, or sixteen-bit fields.
The !NP
Microprocessor instruction set has
been
optimized
for
efficient operations performed directly on the I/O registers.
The INP Microprocessor is designed to facilitate
functions
such
as
logical decision making, indexed branches, and external event
synchronization.
These capabilities allow the !NP Microprocessor
to efficiently perform the functions required of
an
intelligent
network processor.
3-3. Read-Only Memory (ROM)
The !NP has a SK byte, high-speed CMOS/SOS ROM.
The ROM contains
power-on and
reset
programs,
functional
diagnostics,
loader/
dumper routines, and RAM fault location code.
3-4. Random Access Memory (RAM)
The INP has 32K bytes of dynamic
RAM
that stores the
protocol
driver
in use (such as BISYNC point-to-point), the INP's control
program, the HP 3000 interface driver, and data buffers
for
the
communication channel.
Several circuits are required to support and insure the
reliable
operation
of
the RAM.
A refresh circuit is provided to refresh
(or renew) the contents of the dynamic RAM at regular
intervals.
An LSI chip also aids in performing this function.
A parity cir-
cuit calculates a parity bit on each
byte
written
to
RAM
and
verifies the bit on each read from RAM.
Memory-protect circuitry
and separate power supply lines are provided
for
the
RAM,
RAM
refresh
circuitry,
and
other
associated
support circuitry to
assure that no data will be lost in the event of a power
failure
or "brownout".
3-2
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Table of Contents
Troubleshooting
