HP 3457A Service Manual page 190

8-53. Writing to the protected section of RAM U603.
The "Write to CAL-RAM" sequence begins with a CAL command, either from the interface bus or
from the front panel. The microprocessor is reset prior to each calibration routine to insure that valid
measurements are obtained.
Calibration Reset. Upon receiving the CAL command, the microprocessor stops toggling the oTL (U6I1
pin 19) signal and waits for the circuit to time out and reset as follows:
© A continually low (or high) OTL signal applied to capacitor C631 allows the input of inverter
U633A to go low.
© The high output of U633A and the normally high RESET signal applied to the inputs of gate
U633B cause its output to be held low, disabling the reset of counters U631, U632A and
U632B.
© Counters U631, U632A and U632B count the 2 MHz clock signal applied to U631, pin 10.
After counting for 524288 usec. (from the last reset), the output of U632B pin 9 is set high.
© The high output of U632B pin 9 is applied to the minus input of comparator U636B caus-
ing its output to go low. The low output from U636B is applied to the plus input of com-
parator U636C causing its output to go low.
© The low output of U636C is coupled through inverter U634a and U634b to the RESET input
(U6OL pin 37) of the microprocessor; to gate U633b, which causes its output to go high and
reset counters U631, U632a and U632b to zero; and to "flip-flop" U635b. Clearing U635b sets
its @ output high to remove the low signal from the CLR input of U635a, pin 15.
CAL-RAM Lock circuit operation. The CAL-RAM Lock circuit protects the instrument's calibration
constants by preventing accidental writing to the protected (calibration) section of RAM U603. To en-
able the write capability of the protected section of this RAM, memory locations 40 to IFFF. requires
that: 1) the correct address has been placed on the address lines and 2) the CAL-RAM lock circuit has
been "unlocked " (NVE set low).
© After being reset, counters U631, U632 and U632b begin to count the 2 MHz clock signal
applied to U631, pin 10.
© The output of counter U631 (pin 3) is set high 4096 Useconds after the circuit reset. This
signal sets the "J" input of flip-flop U635a high, enables gate U633c, and insures that the out-
put of gate U625c is kept low.
© The microprocessor sets address lines A4 and AS high and line A3 low to select the CALREO
output of decoder U604.
© The timing signal E+a (U604, pin 6) activates the CALREQ output of decoder U604. The CALREG
signal must occur between 4096 and 4100 usec. after the circuit reset has occurred to be valid.
© The negative CALREQ pulse clocks the high "J" input into flip-flop U635a which sets output
signal NVE low. The following section titled CAL-RAM Write Operation explains how this
enables the write input of RAM U603.
If the CALREQ signal is applied to gate U633e while the 4096 usec. signal is low, the
output of U633e will be set high, which resets flip-flop U635b. The low @ output of
HP 3457A Multimeter
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