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CLD-S360, CLD-S26¢
@ PDO154A C603)
On Screen Display
® Block Diagram
| swcser
DISPLAY
ROM
=
BLOCK
127187160 | | |
RAM
10° 24°8
@ Pin Function
Function
TESTIN!
| Test input 1
Input pin for IC test. Normally set to OPEN (with pull-up resistance).
2 | C-SYNC
Composite synchronization input
Inputs composite synchronization signal at negative logic (Schmitt trigger input).
3 | TESTIN2
| Test input 2
Input pin for IC test. Normally set to OPEN (with pull-up resistance).
4 | 2fsc
Master Clock
Inputs clock that is 2 times the color sub-carrier frequency (Schmitt trigger input).
5 | TESTOUT]1)
Test output 2
Output pin to IC test. Normally set to OPEN.
CHA
Channel A output
Outputs character timing at negative logic.
7 | CHB
Channel B output
Outputs logical sum of character timing and blanking timing at negative logic when blanking function
is ON.
VSS
Ground pin
Grounded to GND.
SCK
Serial clock input
Inputs clock for serial communication.
SIN value is read at rise edge (with pull-up resistance, Schmitt trigger input).
10 | SIN
Serial data input
Inputs data for serial communication (with pull-up resistance).
eae
select input
se
to "L" when serial communication is performed (with pull-up resistance).
E
Auto clear input
Initializes internal IC when "L" content of RAM, that stores character code, does not change(with
pull-up resistance, Schmitt trigger input).
ea TESTOUTZ2|
Test output 2
Output pin for IC test. Normally set to OPEN.
Bi 2fsc/256
Master clock 256 division
Outputs clock of master clock (2fsc) that is divided by 256.
15 | VSYNC
V synchronization output
Outputs signal of V synchronization that is separated from pin 2 signal (C-SYNC).
Power pin
Connected to +5V.
63
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