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CLD-S360, CLD-S260
@ PA0023AD (1C401)
FM Detector
@ Pin Function
M PA0058A (C400)
Video Demodulator
@ Pin name
Drop-out pulse output pin
ene
aa Noise reduction 2 input pin
Outputs drop-out pulse if drop out is detected.
117] NRR2
|
H level (during drop-out) > 4.3V
Adjusts noise reduction level using value
Phillips code pulse output pin
H level > 4.3V
L level + 0.2V
Input pin for synchronization separation
Diode clamp input
Clamp level — about 1.9V
21|
DEEM
De-emphasis amplifier output pin
Appropriate feedback circuit is inserted
between this pin and de-emphasis amplifier
input pin.
Output leve] — 1.1 V p-p
De-emphasis amplifier input pin
Input pin for synchronization separation
Input level — 200 mV p-p
oes
Hard-clamped at pedestal level
23| RDOS
DOS frequency sensitivity adjustnent pin
Clamp level —» about 2.7V
Adjusts frequency sensitivity of DOS using
fer fox
sian inser beter spo and OND.
Recommended resistance
20 K2
LPF output pin for synchronization separation
LPF
Output level — 1V p-p (GAIN 0dB)
25)
CINH
a inhibit pin
BOTTOM
| Low side reference voltage pin for A/D
Controls clamp operation of 5, 6, 13 pins
conversions
ov > clamp
RE20K
Resistance pin for internal constant current
5V — clamp inhibit
supply. Connected to 20K Q resistance.
pene = ee
side reference
een pin for A/D
een
5V — output
a Laie
27|
NRINO
Noise reduction 1
Control pin
Output level + 2V p-p (GAIN 6dB)
0V > ON
Synchronization signal level — about 1.67V
5V — OFF
13 | SCLPIN
Synchronization signal clamp input pin
DOS input pin
Input level > 1V p-p
Input level — 500 mV p-p
Clamp level — about 1.67V
| 29 | VCC3
Power pin
14 | NROUT
Noise reduction circuit output pin
Output level > 1.1 V
p-p
OV — output inhibit
Outputs video signal that is clamped by
synchronization chip for A/D conversion.
Phillips code pulse output control pim
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