Table of Contents
Advertisement
CPU 7/7 (RESERVED)
CFG Straps for Processor
PEG Stati c Lane Reve rsal - CFG 2 is for th e 16x
CFG2
1: (Defa ult) Normal Oper ation ; Lan e #
de finit ion m atches sock et pi n map defi nition
0: Lane Rever sed
C F G 2
R 11 1
*1 K _ 0 4
Disp lay P ort Pr esenc e Str ap
1: (Defa ult) Disabl ed; N o Phy sical Disp lay Po rt
CFG4
at tache d to Embedd ed Di splay Port
0: Enabl ed; A n exte rnal Displ ay Po rt de vice i s
co nnect ed to the E mbedd ed Di splay Port
C F G 4
R 11 0
*1 K _ 0 4
PCIE Port Bifur catio n Str aps
11: ( Defau lt) x 16 - Device 1 fu nctio ns 1 and 2 disab led
10: x 8, x8 - De vice 1 func tion 1 ena bled ; func tion 2 dis abled
01: R eserv ed - (Devi ce 1 f uncti on 1 disab led ; funct ion 2 enab led)
CFG[6:5]
00: x 8,x4, x4 - Devic e 1 fu nctio ns 1 and 2 enabl ed
C F G 5
R 99
*1 K _ 0 4
C F G 6
R 92
*1 K _ 0 4
PEG DEFER TRAIN ING
1: (Def ault) PEG T rain immed iatel y fol lowing xxRE SETB de as sertio n
CFG7
0: PEG Wait for BI OS fo r tra ining
C F G 7
R 93
*1 K _ 0 4
R 39 2
3 . 3 V
Sandy Bridge Processor 7/7
( RESERVED )
U 34 E
A K 2 8
C F G 0
C F G [ 0 ]
A K 2 9
A L 2 6
C F G [ 1 ]
C F G 2
C F G [ 2 ]
A L 2 7
A K 2 6
C F G [ 3 ]
C F G 4
C F G [ 4 ]
C F G 5
A L 2 9
A L 3 0
C F G [ 5 ]
C F G 6
C F G [ 6 ]
C F G 7
A M3 1
A M3 2
C F G [ 7 ]
C F G [ 8 ]
A M3 0
A M2 8
C F G [ 9 ]
C F G [ 1 0]
A M2 6
A N 2 8
C F G [ 1 1]
C F G [ 1 2]
A N 3 1
A N 2 6
C F G [ 1 3]
C F G [ 1 4]
A M2 7
A K 3 1
C F G [ 1 5]
C F G [ 1 6]
A N 2 9
C F G [ 1 7]
H _ C P U _ R S V D 1
A J 3 1
V A X G_ V A L _ S E N S E
H _ C P U _ R S V D 2
A H 3 1
V S S A X G_ V A L _ S E N S E
H _ C P U _ R S V D 3
A J 3 3
V C C _ V A L _S E N S E
A H 3 3
H _ C P U _ R S V D 4
V S S _ V A L _ S E N S E
A J 2 6
R S V D 5
V R E F _ C H _A _ D IMM
B 4
D 1
R S V D 6
V R E F _ C H _B _ D IMM
R S V D 7
F 2 5
R S V D 8
F 2 4
F 2 3
R S V D 9
R S V D 1 0
D 2 4
G2 5
R S V D 1 1
R S V D 1 2
G2 4
E 2 3
R S V D 1 3
R S V D 1 4
D 2 3
C 3 0
R S V D 1 5
R S V D 1 6
A 3 1
R S V D 1 7
B 3 0
R S V D 1 8
B 2 9
R S V D 1 9
D 3 0
R S V D 2 0
B 3 1
R S V D 2 1
A 3 0
R S V D 2 2
C 2 9
R S V D 2 3
J 2 0
R S V D 2 4
B 1 8
R S V D 2 5
A 1 9
V C C I O_ S E L
J 1 5
R S V D 2 7
10/29
P Z 9 8 8 27 -3 6 4B - 01 F
10 K _ 0 4
R 3 9 1
* 10 m i l _ 0 4
H _S N B _ I V B # _P W R C TR L
On C RB
H_SN B_IVB #_PWR CTRL = low, 1.0V
H_SN B_IVB #_PWR CTRL = high /NC, 1.05V
[ 2, 3 ,1 1 , 13 , 1 4 , 1 5, 1 7 , 1 8, 19 , 2 0 , 22 , 2 3 , 2 6, 2 8 , 3 0, 3 1 ,3 3 ,34 ,3 5 ]
L 7
R S V D 28
A G 7
R S V D 29
A E 7
R S V D 30
A K 2
R S V D 31
W 8
R S V D 32
A T 2 6
R S V D 33
A M 3 3
R S V D 34
A J 2 7
R S V D 35
T 8
R S V D 37
J 1 6
R S V D 38
H 16
R S V D 39
G 16
R S V D 40
A R 3 5
R S V D 41
A T 3 4
R S V D 42
A T 3 3
R S V D 43
A P 3 5
R S V D 44
A R 3 4
R S V D 45
B 3 4
R S V D 46
A 3 3
R S V D 47
A 3 4
R S V D 48
B 3 5
R S V D 49
C 35
R S V D 50
1 . 5 V
R 4 0
* 0 _0 4
A J 3 2
R S V D 51
A K 3 2
R 3 8
R S V D 52
Q 7
1K _ 1 % _ 04
* A O3 4 0 2L
A H 2 7
S
D
V R E F _ C H _ A _ D I MM
MV R E F _ D Q _ D I M 0
V C C _ D I E _ S E N S E
R 3 9
R 3 1
10/29
A N 3 5
R S V D 54
A M 3 5
*1 K _ 0 4
1K _ 1 % _ 04
R S V D 55
D R A M R S T _ C N TR L
D R A M R S T _ C N TR L [ 3, 14 ]
A T 2
R S V D 56
A T 1
R S V D 57
A R 1
1 . 5 V
R S V D 58
R 4 4
* 0 _0 4
B 1
R 28
K E Y
Q 6
* A O3 4 0 2L
1 K _ 1% _ 0 4
S
D
V R E F _ C H _ B _ D I MM
M V R E F _ D Q_ D I M 1
10/29
R 4 9
R 29
*1 K _ 0 4
1 K _ 1% _ 0 4
D R A M R S T _ C N TR L
[ 3 , 6 , 9, 1 0 , 2 0, 2 6 ,2 8 ,31 ,3 3 ]
1 . 5V
3 . 3V
Schematic Diagrams
Sheet 8 of 43
CPU 7/7
(RESERVED)
M V R E F _D Q_ D I MMA
[ 9]
M V R E F _D Q_ D I MMB
[ 10 ]
CPU 7/7 (RESERVED) B - 9
Advertisement
Table of Contents
