Clevo ITAUTEC W244HUQ Series Service Manual page 58

Schematic Diagrams
CPU 2/7 (CLK, MISC, JTAG)
PU/PD for JTAG signals
1. 0 5 V S _ V T T
3 . 3V S
Sheet 3 of 43
CPU 2/7
(CLK, MISC, JTAG)
[ 17 , 2 3 ] P L T_ R S T #
B - 4 CPU 2/7 (CLK, MISC, JTAG)
Sandy Bridge Processor 2/7
XD P _ TM S
R 41 6 5 1 _ 04
R 10 8 5 1 _ 04 XD P _ TD I _ R
XD P _ P R E Q #
R 10 9 * 51 _ 0 4
R 41 5 5 1 _ 04 XD P _ TD O_ R
XD P _ TC L K
R 41 4 5 1 _ 04
R 95 5 1 _ 04 XD P _ TR S T #
H _ S N B _ I V B #
[ 18 ] H _S N B _ I V B #
R 40 7 1 K _ 0 4 XD P _ D B R _R
H _ C A TE R R #
R 4 1 1 *1 0 mi l _ 04 H _ P E C I _ R
[ 1 8 , 27 ] H _ P E C I
H _ P R OC H O T# _ D
R 4 0 5 5 6 _1 % _ 04
[ 3 6] H _ P R O C H OT #
If P RO CH OT # i s no t us ed, t he n it m ust
be t er mi na ted w it h a 68- O +- 5% p ul l-u p
re si st or t o 1 .0 5V S_ VT T .
H _ T H R MT R I P #_ R
R 4 1 7 *1 0 mi l _ 04
[ 1 8 ] H _ T H R MT R I P #
R 4 1 9 *1 0 mi l _ 04 P M_ S Y N C _R
[ 1 5 ] H _ P M _S Y N C
R 4 1 8 *1 0 mi l _ 04 H _ C P U P W R GD _ R
[ 1 8] H _ C P U P W R G D
P M S Y S _ P W R GD _ B U F R 60 1 3 0_ 1 % _0 4 V D D P W R GO OD _ R
Buffered reset to CPU
1 . 0 5 V S _ V T T B U F _C P U _ R S T#
R 1 0 5 7 5_ 1 % _0 4 R 1 04 43 _ 1 %_ 0 4
11/ 04
6
3 . 3 V S D
Q3 6 A
R 5 3 0 1 0K _ 0 4 2 G MT D N 7 0 02 Z H S 6 R
S
3 1
D
5 G Q3 6 B
S MT D N 7 0 02 Z H S 6 R
4
R 1 12 *1 . 5K _1 % _ 04
[ 2 7 ] H _ P R OC H O T_ E C
R 5 3 1 C 9 6 R 10 6
1 0/1
1 00 K _ 0 4 *6 8 p _5 0 V _ N P O _ 04 *7 5 0_ 1 % _0 4
C AD N ote: Capa cito r
n eed to be pla ced
c lose to b uffe r ou tput pin
( CLK,MISC,JTAG )
U 3 4 B
A 28
B C LK
C 2 6 A 27
P R O C _ S E L E C T # B C L K #
A N 3 4
S K T OC C #
A 16
D P L L _R E F _ S S C LK
A 15
D P L L _ R E F _ S S C L K #
A L 3 3
C A T E R R #
A N 3 3 R 8 C P U D R A MR S T #
P E C I S M_ D R A MR S T #
A L 3 2 A K 1 S M_ R C O MP _ 0
P R O C H OT # S M _ R C OMP [ 0] A 5
S M_ R C O MP _ 1
S M _ R C OMP [ 1]
A 4 S M_ R C O MP _ 2
S M _ R C OMP [ 2]
A N 3 2
TH E R M T R I P #
A P 2 9 X D P _ P R D Y #
P R D Y #
A P 2 7 X D P _ P R E Q#
P R E Q #
A R 2 6 X D P _ T C L K
T C K
A R 2 7 X D P _ T MS
T MS
A M 3 4 A P 3 0
X D P _ T R S T #
P M_ S Y N C TR S T #
A R 2 8
X D P _ T D I _ R
T D I
A P 2 6 X D P _ T D O _R
A P 3 3 T D O
U N C OR E P W R GO OD
A L3 5 X D P _ D B R _ R
V 8 D B R #
S M_ D R A MP W R O K
A T2 8
X D P _ B P M 0_ R
B P M # [ 0]
A R 2 9 X D P _ B P M 1_ R
B P M # [ 1] A R 3 0
X D P _ B P M 2_ R
B P M # [ 2]
A R 3 3 A T3 0 X D P _ B P M 3_ R
R E S E T # B P M # [ 3] A P 3 2
X D P _ B P M 4_ R
B P M # [ 4]
A R 3 1 X D P _ B P M 5_ R
B P M # [ 5] A T3 1
X D P _ B P M 6_ R
B P M # [ 6]
A R 3 2 X D P _ B P M 7_ R
B P M # [ 7]
P Z 98 8 2 7-3 6 4 B -0 1F
10/29
H _ P R OC H OT #
Q1 4
G
MT N 70 0 2 Z H S 3 C 51 5
4 7 p_ 5 0 V _ N P O _0 4
R 9 1 1 0 0 K _ 04
R 9 0 * 0 _0 4
[ 2 , 5 , 1 8, 1 9 , 2 0 , 34 , 3 6 ]
[ 6 , 8 , 9, 1 0 , 2 0, 2 6 , 2 8 , 31 , 3 3 ]
[ 2, 8 , 1 1 , 13 , 1 4 , 1 5, 1 7 , 1 8, 19 , 2 0 , 22 , 2 3 , 2 6, 2 8 , 3 0, 3 1 , 3 3 , 34 , 3 5 ]
[ 9, 1 0 , 1 1 , 12 , 1 3 , 14 , 1 5 , 1 6, 1 7 , 1 8, 19 , 2 0 , 23 , 2 4 , 2 5, 2 7 , 2 8, 2 9 , 3 0 , 31 , 3 6 ]
Processor Pullups/Pull downs
1 . 05 V S _ V T T
H _P R O C H O T # R 41 0 62 _ 0 4
H _C P U P W R G D _ R
R 41 2 10 K _ 0 4
C 58 5 * 0. 1 u _ 10 V _ X 7 R _ 0 4
11/0 3
TRA CE W ID TH 1 0MI L, L EN GT H < 50 0M IL S
C L K _ E XP _P [ 14 ] DDR3 Compensation Signals
C L K _ E XP _N [ 1 4]
S M _ R C OMP _0
R 41 3 1 4 0_ 1 % _ 04
C L K _ D P _ P [ 1 4 ]
S M _ R C OMP _1
R 38 2 2 5 . 5 _1 % _ 04
C L K _ D P _ N [ 14 ]
S M _ R C OMP _2 R 38 1 2 0 0_ 1 % _ 04
S3 circuit:- DRAM PWR GOOD logic
3 . 3V 1 . 5 V _ C P U
10/2 8
R 7 3 R 57
*2 0 0_ 1 % _0 4 1 0 K _ 04
D 2 0
1 A
[ 1 5] P M_ D R A M_ P W R GD
3
C P MS Y S _P W R G D _ B U F
2 A
[ 1 5, 3 3 ] 1 . 8 V S _ P W R G D
*B A T5 4 A W G H
R 58
* 39 _ 0 4
R 5 9 0 _ 04
Q 10
G
[ 6 , 3 1, 3 3 , 3 4 ] S U S B
* MT N 7 0 0 2Z H S 3
S3 circuit:- DRAM_RST# to memory
should be high during S3
1 . 5V
R 4 7 *0 _0 4 R 4 5
1K _ 0 4
Q8
MT N 70 0 2 Z H S 3
C P U D R A M R S T # S D
R 48 1K _0 4
D D R 3_ D R A M R S T # [ 9 , 10 ]
R 4 6
D R A M R S T _ C N TR L [ 8 , 14 ]
C 2 2
0 . 0 47 u _ 10 V _ X 7R _ 04
1 . 05 V S _ V T T
[ 6 , 3 1 ] 1 . 5V _C P U
1 . 5V
3 . 3V
3 . 3V S