Integra PLA-50FP1 Manual page 105

(3) PAL/NTSC decoding
After passing through the built-in delay line of IC5504, the Y signal is then output from Pin 4. This signal is
applied to Pin 15 of IC5503 (CTI) and double-amplified there. The resultant output is then generated from
Pin 2. The output signal of Pin 2 passes through DL5501 and IC5501, and is then returned to Pin 53 of
IC5504. It is further led to the internal RGB matrix through the pedestal clamp, black expander, DC repro-
duction, sharpness circuit, etc.
IC5504
Pin 15
VIDEO
Signal Y
CHROMA
The C signal is processed for system discrimination. When it is defined for the PAL or NTSC, it is then
processed through the APC circuit, ACC circuit, carrier reproduction, and the phase detection circuit to
make up the R-Y/B-Y signals. The signal output is once generated from Pin 5 and Pin 6, and then entered
in Pins 12/13 of IC5510 (SECAM decoding). After passing through the internal switch, the outputs are
generated from Pins 10 and 11, and sequentially entered in the next stage.
[In regard to information for system discrimination, the control signal output is generated from Pins 3 and 7
of IC5504, in order to control IC5510 (SECAM decoding) and IC5508 (1H DELAY).]
In IC5508 (1H DELAY), the signal is amplified and its output is generated from Pins 29 and 30. This output
is applied to Pins 7 and 8 of IC5503 (CTI).
Internal color processing is conducted in IC5504, and the resultant output is fed to the RGB matrix.
At the RGB matrix stage, this chrominance signal and the foregoing brightness signal are used to generate
the analog RGB signal at the RGB matrix stage.
IC5504
Pin 13
VIDEO
CHROMA
Signal C
Frow of Signal Y
IC5503
Pin 4 CTI
Pin 15
Pin 53
Frow of Signal C
Signal R-Y/B-Y
IC5510
SECAM
DEMO
Pin 51/52
5
DL5501/IC5501
(Delay line/SW)
Pin 2
Signal R-Y/B-Y Signal R-Y/B-Y
IC5509
1HDELAY
Signal R-Y/B-Y
IC5503
CTI