Denon DCT-950R Service Manual page 45

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Functioin
XRAOF output at PSSL = 0.
MNTS output at PSSL = 0.
MNT2 output at PSSL = 0.
MNT1 output at PSSL = 0.
MNTO output at PSSL = 0.
X'tal oscillation circuit input . L at X'tal is 16.9344MHz H at X'tal is 33.8688MHz.
X'tal selection input terminal. L at X'tal is 16.9344MHz, H at X'tal is 33.8688MHz.
2/3 divided output. Does not vary with variable pitch.
4.2336MHz output. Simultaneously varies when variable pitched.
16.9844MHz output. Simultaneously varies when variable pitched.
Digital-out ON/OFF control terminal (L._ = OFF, H = ON).
Emphasis mode output of playback disc (L = with emphasis, H = without emphasis).
Sub-code sync output terminal (H at either of sub-code sync SO or $1 is detected).
SubQ 80-bit output. PCM peak data, level data 16-bit output.
n
Q
QO A
DFCT measure circuit OFF at H).
By sampling GFS with 460Hz and when GFS at H, H output. L output at consecutively L 8 times.
Terminal for disc innermost circle detection signal.
Pin No. Symbol VO
57 DAO5S {e) DAOS5 output at PSSL = 1.
58 DAO4 O DAO4 output at PSSL = 1.
59 DAO03 {e) DAOS output at PSSL = 1.
60 DA02 oO DAO2 output at PSSL = 1.
61 DAO1 Oo DAO1 output at PSSL = 1.
62 XTAI {
63 XTAO ie) Xtal oscillation circuit output.
64 XTSL 1
65 Vss _ Digital GND.
66 FST |__| 2/3 divided input of terminals 62, 63.
67 FSTO oO
68 C4M (e)
69 C16M ie)
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71 DOUT {e) Digital-out output terminal.
72 EMPH ie)
73 WFCK ie) WEFCK output.
O
75 SBSO O Serial output of sub P ~ W.
76 EXCK I Clock input for SQSO read out.
SQSO O
Clock input for SQSO read out.
MUTE I Mute shifting terminal (mute at H).
| 80 __| SENS © _|_SENS output. Emits to CPU.
XRST I System reset (reset at L).
: | e2 |oiRe {| t | Using at 1 track jump.
Clock or SENS serial data read out.
Terminal for DECT shifting
Terminal for anti-shock.
| se |oata- | 1 | Serial data input from CPU.
XLAT Latch input from CPU.
CLOK am Serial data transfer clock input from CPU.
| _s9 {cour | o | Number of track count signal output.
90 Vpp = Digital power supply.
91 MIRR {e) Mirror signal output.
- 92 DFCT (0) Defect signal output.
93 FOK {| O Focus OK output.
94 FSW oO Output filter shifting output of spindle motor.
95 MON Oo ON/OFF control output of spindle motor.
96 MDP Oo Servo control of spindle motor.
97 oO Servo control of spindle motor.
oO
|
Oo Sled rive output.
Note:
@ 64-bit slot is 2's compliment output of LSB first, 48-bit slot is 2's compliment output.
® CTOP monitors frame sync protection condition (H: sync protection window open).
® XUGF is frame sync possessed from EFM signal and is negative pulse, Signal previous to sync protection.
@ XPLCK is reversal of PLL clock. PLL is so made up to coincide rising edge with the varying point of EFM signal.
© GFS signal is a signal to become H when frame sync coincides inserted protection timing.
® RFCK is possessed with X'tal accuracy. Signal of 136us cycle.
= ® C2PO is a signal indicating data error condition. ;
® XRAOR is a generating signal when 32kRAM exceeds jitter margin of 28 frame.
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