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Chapter 1
Getting Started
System Timing Slot
The System Timing Slot is slot 10. The system timing slot will accept the following peripheral
modules:
•
A PXI Express System Timing Module with x4 or x1 PCI Express link to the system slot
through a PCIe switch.
•
A PXI Express Peripheral with x4 or x1 PCI Express link to the system slot through a PCIe
switch.
•
A CompactPCI Express Type-2 Peripheral with x4 or x1 PCI Express link to the system slot
through a PCIe switch.
The system timing slot has 3 dedicated differential pairs (PXIe_DSTAR) connected from the
TP1 and TP2 connectors to the XP3 connector for each PXI Express peripheral or hybrid
peripheral slot, as well as routed back to the XP3 connector of the system timing slot as shown
in Figure 1-4. The PXIe_DSTAR pairs can be used for high-speed triggering, synchronization
and clocking. Refer to the PXI Express Specification for details.
The system timing slot also has a single-ended (PXI Star) trigger connected to every slot. Refer
to Figure 1-4 for details.
The system timing slot has a pin (PXI_CLK10_IN) through which a system timing module may
source a 10 MHz clock to which the backplane will phase-lock. Refer to the
Clock
section for details.
The system timing slot has a pin (PXIe_SYNC_CTRL) through which a system timing module
can control the PXIe_SYNC100 timing. Refer to the PXI Express Specification and the
PXIe_SYNC_CTRL
section of this chapter for details.
Figure 1-4. PXIe_DSTAR and PXI Star Connectivity Diagram
PXI Star 8
PXI Star 7
PXI Star 6
PXI Star 5
PXI Star 4
PXIe_DStar 4
PXIe_DStar 7
PXIe_DStar 5
PXIe_DStar 6
H
H
H
H
2
3
4
5
6
1
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PXI Star 3
PXI Star 2
PXI Star 1
PXI Star 11
PXI Star 0
PXI Star 10
PXIe_DStar 0
PXIe_DStar 1
PXIe_DStar 9
PXIe_DStar 2
PXIe_DStar 10
PXIe_DStar 3
PXIe_DStar 11
7
8
9
10
11
12
0
System Reference
PXI Star 17
PXI Star 16
PXI Star 15
PXI Star 14
PXI Star 13
PXI Star 12
PXIe_DStar 12
PXIe_DStar 16
PXIe_DStar 13
PXIe_DStar 14
PXIe_DStar 15
H
H
H
13
14
15
16
17
18
H
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