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7.1 SPI 2
The 96Boards specification calls for one SPI bus master to be provided on the Low Speed Expansion Connector.
The RZ/G2L100&RZ/V2L100 implements a full SPI master with 4 wires, CLK, CS, MOSI and MISO all connect directly to
the RZ/G2L&RZ/V2L SoC. These signals are driven at 1.8V.
7.2 GPIO {V,W,X,Y}
The 96Boards specifications calls for 4 GPIO lines to be implemented on the High Speed Expansion Connector 2.
The RZ/G2L100&RZ/V2L100 implements this requirement. 4 GPIOs are routed to the RZ/G2L&RZ/V2L SoC .
GPIO V - Connects to P47_2 of RZ/G2L&RZ/V2L SoC, It is a 1.8V signal
GPIO W - Connects to P47_3 of RZ/G2L&RZ/V2L SoC. It is a 1.8V signal
GPIO X - Connects to P14_0 of RZ/G2L&RZ/V2L SoC. It is a 1.8V signal.
Room 02-04, 10/F, Block A, Building 8, Shenzhen International Innovation Valley, Dashi Road,
Nanshan District, Shenzhen, Guangdong, China
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GND
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GND
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GND
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GND
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GND
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GND
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GND
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HS2_SPI2_CLK
HS2_SPI2_CS
HS2_SPI2_MOSI
HS2_SPI2_MISO
HS2_GPIO_V
HS2_GPIO_W
HS2_GPIO_X
HS2_GPIO_Y
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GND
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