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The 96Boards specification calls for a MIPI-DSI to be present on the High Speed Expansion Connector. A minimum of
one lane is required and up to four lanes can be accommodated on the connector.
The RZ/G2L100&RZ/V2L100 implementation supports a full four lane MIPI-DSI interface that is routed to the High
Speed Expansion Connector. Since the RZ/G2L&RZ/V2L has only single MIPI-DSI interface and it may be used to drive
the DSI-HDMI Bridge, DSI muxing is required. A muxing device, U24 (FSA644UCK) is used on the board. Only one
interface, HDMI, or the Expansion MIPI-DSI can be active at a given time. The controlling signal is named
'P4_1_DSI_SW_SEL'. When this signal is logic high, '1', the MIPI-DSI is routed to the DSI-HDMI Bridge.When
'P4_1_DSI_SW_SEL' is logic level low, '0', the MIPI-DSI is routed to the High Speed Expansion connector. This design
assigned the 'P4_1_DSI_SW_SEL' function to P4_1.
6.2 MIPI CSI 0
Renesas RZ/G2L&RZ/V2L supports one 4-lane CSI1 port which used to connect high speed expansion connector as per
96boards standard.
6.3 I2C{2/3}
The 96Boards specification calls for two I2C interfaces to be present on the High Speed Expansion Connector. Both
interfaces are optional unless a MIPI-CSI interface has been implemented. Then an I2C interface shall be implemented.
The current RZ/G2L100&RZ/V2L100 implementation supports two MIPI-CSI interfaces and therefore must support two
I2C interfaces. for MIPI-CSI0 the companion I2C2 is routed directly from the Renesas RZ/G2L&RZ/V2L.
6.4 SD1
The 96Boards specification calls for an SD interface port to be part of the High Speed Expansion Connector.
The Renesas RZ/G2L100&RZ/V2L100 implements a full SD master, CLK, CMD, DAT(3:0) all connect directly to the
RZ/G2L&RZ/V2L SoC. These signals are driven at 1.8V.
6.5 Clocks
The 96Boards specification calls for one or two programmable clock interfaces to be provided on the High Speed
Expansion Connector. These clocks may have a secondary function of being HS1_CLK0 and HS1_CLK1, If these clocks
can't be supported by the SoC than an alternative GPIO or No-Connect is allowed by the specifications.
The Renesas RZ/G2L100&RZ/V2L100 implements two CSI clocks, HS_CLK0 via RZ/G2L&RZ/V2L P39_0 and HS_CLK1 via
RZ/G2L&RZ/V2L P39_1. These signals are driven at 1.8V.
6.6 USB
The 96Boards specification calls for a USB Data line interface to be present on the High Speed Expansion Connector.
The RZ/G2L100&RZ/V2L100 implements this requirements by routing USB channel 3 from the USB HUB to the High
Speed Expansion Connector.
7 60-pin High Speed(HS2) expansion connector
The following tables show the High Speed Expansion Connector pin out:
Pin No.
Pin definition
Pin No.
Pin definition
Room 02-04, 10/F, Block A, Building 8, Shenzhen International Innovation Valley, Dashi Road,
Nanshan District, Shenzhen, Guangdong, China
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