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AGND
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AGND
4.1 UART{0/1}
The 96Boards specifications calls for a 4-wire UART implementation, UART0 and an optimal second 2-wire UART, UART1
on the Low Speed Expansion Connector.
The RZ/G2L100&RZ/V2L100 implements UART0 as a 4-wire UART that connects directly to the RZ/G2L&RZ/V2L SoC.
These signals are driven at 1.8V.
The RZ/G2L100&RZ/V2L100 implements UART1 as a 2-wire UART that connects directly to the RZ/G2L&RZ/V2L SoC.
These signals are driven at 1.8V.
4.2 I2C{0/1}
The 96Boards specification calls for two I2C interfaces to be implemented on the Low Speed Expansion Connector.
The RZ/G2L100&RZ/V2L100 implements both interfaces, I2C0 and I2C1 that connects directly to the RZ/G2L&RZ/V2L
SoC. A 2K resistor is provided as pull-up for each of the I2C lines per the I2C specifications, these pull-ups are connected
to the 1.8V voltage rail.
4.3 GPIO{A-L}
The 96Boards specifications calls for 12 GPIO lines to be implemented on the Low Speed Expansion Connector. Some of
these GPIOs may support alternate functions for DSI/CSI control
The RZ/G2L100&RZ/V2L100 implements this requirement. 12 GPIOs are routed to the RZ/G2L&RZ/V2L SoC .
GPIO A - Connects to P48_2 of RZ/G2L&RZ/V2L SoC, It is a 1.8V signal
GPIO B - Connects to P43_0 of RZ/G2L&RZ/V2L SoC. It is a 1.8V signal
GPIO C - Connects to P3_0 of RZ/G2L&RZ/V2L SoC. It is a 1.8V signal.
GPIO D - Connects to P43_1 of RZ/G2L&RZ/V2L SoC. It is a 1.8V signal.
GPIO E - Connects to P3_1 of RZ/G2L&RZ/V2L SoC. It is a 1.8V signal.
GPIO F - Connects to P43_2 of RZ/G2L&RZ/V2L SoC. It is a 1.8V signal.
GPIO G - Connects to P19_1 of RZ/G2L&RZ/V2L SoC. It is a 1.8V signal.
GPIO H - Connects to P42_2 of RZ/G2L&RZ/V2L SoC. It is a 1.8V signal.
GPIO I - Connects to P47_0 of RZ/G2L&RZ/V2L SoC. It is a 1.8V signal.
GPIO J - Connects to P10_1 of RZ/G2L&RZ/V2L SoC. It is a 1.8V signal.
GPIO K - Connects to P43_3 of RZ/G2L&RZ/V2L SoC. It is a 1.8V signal.
GPIO L - Connects to P11-0 of RZ/G2L&RZ/V2L SoC. It is a 1.8V signal.
4.4 SPI 0
The 96Boards specification calls for one SPI bus master to be provided on the Low Speed Expansion Connector.
The RZ/G2L100&RZ/V2L100 implements a full SPI master with 4 wires, CLK, CS, MOSI and MISO all connect directly to
the RZ/G2L&RZ/V2L SoC. These signals are driven at 1.8V.
4.5 I2S
The 96Boards specification calls for one I2S bus to be provided on the Low Speed Expansion Connector. The CLK, FS and
DO signals are required while the DI is optional.
Room 02-04, 10/F, Block A, Building 8, Shenzhen International Innovation Valley, Dashi Road,
Nanshan District, Shenzhen, Guangdong, China
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