Chipset Overview - Supermicro X6DVL-iG2 User Manual

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Chipset Overview

Built upon the functionality and the capability of the E7320 chipset, the
X6DVL-INF/X6DVL-iG2 motherboard provides the performance and feature
set required for dual processor-based servers, with configuration options
optimized for communications, storage, computation and clustering applica-
tions. The Intel E7320 chipset
E7320 Memory Controller Hub (MCH) and the I/O Controller Hub (6300ESB
ICH).
The E7320 MCH supports single or dual Xeon EM64T processors with Front
Side Bus speeds of up to 800 MHz(*Note). Its memory controller provides
direct connection to two channels of registered DDR2 400 with a marched
system bus address and data bandwidths of up to 6.4GB/s. The E7320
also supports the new PCI Express high speed serial I/O interface for supe-
rior I/O bandwidth. The MCH provides configurable x8 PCI Express inter-
faces which may alternatively be configured as two independent x4 PCI
Express interfaces. These interfaces support connection of the MCH to a
variety of other bridges that are compliant with the PCI Express Interface
Specification, Rev. 1.0a. The MCH interfaces with the 6300ESB I/O Control-
ler Hub (6300ESB ICH) via Hub Interface.
6300 ESB ICH System Features
In addition to providing the I/O subsystem with access to the rest of the
system, the 6300ESB ICH I/O Controller Hub integrates many I/O functions.
The 6300ESB ICH I/O Controller Hub integrates: 2-channel Ultra ATA/100
Bus Master IDE Controller, two Serial ATA (SATA) Host Controllers, SMBus
2.0 Controller, LPC/Flash BIOS Interface, PCI (66MHz) Interface, PCI 2.2
Interface and System Management Controller.
(*Notes: 1. The CPU FSB speed is set at 800 MHz by the Manufacturer.
Please do not change the CPU FSB setting. 2. All components related to
the InfiniBand are available on the X6DVL-INF only.)
consists of the following components: the
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Chapter 1: Introduction