Mainboard Features - Supermicro SUPERSERVER 6013P-8 User Manual

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UPER ERVER 6013P-8 Manual
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One (1) CD-ROM containing drivers and utilities:
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SuperServer 6013P-8 User's Manual
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Mainboard Features

At the heart of the SuperServer 6013P-8 lies the X5DPR-8G2+, a dual Intel
Xeon processor serverboard designed to provide maximum performance.
Below are the main features of the X5DPR-8G2+.
Chipset
The X5DPR-8G2+ is based on Intel's E7501 chipset, which is a high-perfor-
mance chipset designed for dual-processor servers (see Figure 1-1).
The E7501 chipset consists of four major components: the Memory Control-
ler Hub (MCH), the I/O Controller Hub 3 (ICH3), the PCI-X 64-bit Hub 2.0
(P64H2) and the 82808AA Host Channel Adapter (VxB).
The MCH has four hub interfaces, one to communicate with the ICH3 and
three for high-speed I/O communications. The MCH employs a 144-bit wide
memory bus for a DDR-266 (PC2100) memory interface, which provides a
total bandwidth of up to 4.2 GB/s.
point-to-point connection using an 8-bit wide, 66 MHz base clock at a 4x
data transfer rate. The P64H2 interface is a 1 GB/s point-to-point connec-
tion using a 16-bit wide, 66 MHz base clock at a 8x data transfer rate.
The ICH3 I/O Controller Hub provides various integrated functions, including
a two-channel UDMA100 bus master IDE controller, USB host controllers, a
System Management Bus controller and an AC'97 compliant interface.
The P64H2 PCI-X Hub provides a 16-bit connection to the MCH for high-
performance IO capability and the 64-bit PCI-X interface.
The ICH3 interface is a 266 MB/sec
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