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6-3-5 Scaler Borad
1. PW364 Input Clock
(1) MCKEXT
Check IC406(IC502) pin 5.
Power on : MCKEXT = 97.5MHz
Standby : MCKEXT = 48.75MHz
(2) MCKEXT, DCKEXT
Check IC407(ICS502) pin 25. DCKEXT = 65MHz
(3) VCLK
Check IC203(SDA9400) pin 26. VCLK = 27MHz
(4) GCLK
Check IC401(AD9884) pin 115(TP404).
GCLK is differently seen according to PC input signal format(VGA, SVGA, XGA)
GCLK = 15MHz ~ 50MHz(This value is apparently half of the clock frequency of the relevant PC input signal format.
2. VPC3230
- Check power is supplied(5V, 3.3V).
- Check Reset(pin 15) is high.
- Check I
2
C-bus(pins 13, 14)
- Check the signal input to Y signal(pin73), C signal(pin 71), PLL DVD-Y signal (pin 72).
- Check the output clocks LLC1(pin 28), LLC2(pin 27). (LLC1 = 13.5MHz, LLC2 = 27MHz)
- Check the output H sync(pin 56) and check V sync(pin 57) is output.
- Check output digital data.
3. SDA9400
- Check power is supplied(3.3V).
- Check Reset(pin 30) is high.
- Check I
2
C-bus(pins 20, 21)
- Check clock is input.(pins 28, 54 : 27MHz. pin 29 : 13.5MHz)
- Check digital data input.
- Check the input H sync (pin 23) = 15.75MHz, V sync (pin 22) = 60Hz
- Check digital data input.
- Check the output H sync (pin 60) = 31.5KHz, V sync (pin 61) = 60Hz, VCLK (pin 26) = 27MHz
4. AD9884(IC101)
- Check power is supplied(3.3V)
- Check I
2
C-bus(pins 29, 30)
- Check PC signal, HD-component signal is input.
- Check the input signal GREF (pin 40). The GREF signal applies to a fixed form of the input H sync signal.
- Check the output signal GFBK (pin 117). The GFBK signal applies to a fixed form of PLLD H sync signal.
- Check the output signal GCLK (pin 115). The GCLK is differently seen according to the PC input signal format(VGA, SVGA, XGA).
GCLK = 15MHz ~ 50MHz This value is apparently half of the clock frequency of the relevant PC input signal format.
- Check digital data output.
Samsung Electronics
Troubleshooting
6-7
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