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GigaDevice Semiconductor GD32E502 Series User Manual

GigaDevice Semiconductor GD32E502 Series User Manual

Arm cortex-m33 32-bit mcu

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GigaDevice Semiconductor Inc.

GD32E502xx

®

Arm

Cortex

-M33 32-bit MCU

®

User Manual

Revision 1.1

(Sep. 2023)

Table of Contents

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Summary of Contents for GigaDevice Semiconductor GD32E502 Series

Page 1 GigaDevice Semiconductor Inc. GD32E502xx ® Cortex -M33 32-bit MCU ® User Manual Revision 1.1 (Sep. 2023)
Page 2: Table Of Contents
GD32E502xx User Manual Table of Contents Table of Contents......................... 2 List of Figures ........................16 List of Tables ........................22 1. System and me mory architecture ................25 ® ® 1.1. Cortex -M33 processor...................25 1.2. System architecture ....................26 1.3. Memory map......................28 1.3.1.
Page 3 GD32E502xx User Manual 2.3.7. Mass erase ......................58 2.3.8. Main flash programming ..................59 2.3.9. Main Flash Fast Programming..................61 2.3.10. Check blank command....................64 2.3.11. OTP programming....................64 2.3.12. Shared RAM ......................64 2.3.13. Data Flash operation ....................65 2.3.14. Emulated EEPROM ....................66 2.3.15. Option bytes 0 erase....................67 2.3.16.
Page 4 GD32E502xx User Manual 3.4.1. Control register (PMU_CTL) .................. 102 3.4.2. Control and status register (PMU_CS) ..............103 4. Backup registers (BKP).................... 106 4.1. Overview......................... 106 4.2. Characteristics ....................... 106 4.3. Function overview....................106 4.3.1. RTC clock calibration .................... 106 4.3.2. Tamper detection ....................
Page 5 GD32E502xx User Manual 6.2. Characteristics ....................... 147 6.3. Interrupts function overview.................. 147 6.4. External interrupt and event (EXTI) block diagram ..........151 6.5. External Interrupt and Event function overview............ 151 6.6. Register definition....................154 6.6.1. Interrupt enable register (EXTI_INTEN) ..............154 6.6.2.
Page 6 GD32E502xx User Manual 8.3.1. GPIO pin configuration ..................180 8.3.2. External interrupt/event lines .................. 180 8.3.3. Alternate functions (AF)..................180 8.3.4. Additional functions ....................180 8.3.5. Input configuration....................181 8.3.6. Output configuration ..................... 181 8.3.7. Analog configuration ..................... 182 8.3.8. Alternate function (AF) configuration ...............
Page 7 GD32E502xx User Manual 9.5.6. Shifter status interrupt enable register (MFCOM_SSIEN) ........... 217 9.5.7. Shifter error interrupt enable register (MFCOM_SEIEN) ..........217 9.5.8. Timer status interrupt enable register (MFCOM_TMSIEN) .......... 218 9.5.9. Shifter status DMA enable register (MFCOM_SSDMAEN) .......... 218 9.5.10. Shifter control x register (MFCOM_SCTLx) .............. 219 9.5.11.
Page 8 GD32E502xx User Manual 11.5.3. Channel x control register (DMA_CHxCTL) .............. 241 11.5.4. Channel x counter register (DMA_CHxCNT)............. 243 11.5.5. Channel x peripheral base address register (DMA_CHxPADDR) ......... 244 11.5.6. Channel x memory base address register (DMA_CHxMADDR) ........244 DM A request multiplexer (DMAMUX) ..............246 12.1.
Page 9 GD32E502xx User Manual 14.2. Characteristics ....................268 14.3. Pins and internal signals ..................269 14.4. Function overview ....................270 14.4.1. Foreground calibration function ................270 14.4.2. ADC clock ......................271 14.4.3. ADC enable......................271 14.4.4. Routine sequence ....................271 14.4.5. Operation modes ....................271 14.4.6.
Page 10 GD32E502xx User Manual 15.3. Function overview ....................298 15.3.1. DAC enable......................298 15.3.2. DAC output buffer ....................298 15.3.3. DAC data configuration ..................298 15.3.4. DAC trigger ......................298 15.3.5. DAC workflow ...................... 299 15.3.6. DAC noise wave ....................299 15.3.7.
Page 11 GD32E502xx User Manual 17.4.4. RTC prescaler low register (RTC_PSCL) ..............324 17.4.5. RTC divider high register (RTC_DIVH) ..............324 17.4.6. RTC divider low register (RTC_DIVL) ..............324 17.4.7. RTC counter high register (RTC_CNTH) ..............325 17.4.8. RTC counter low register (RTC_CNTL)..............325 17.4.9.
Page 12 GD32E502xx User Manual 19.3.12. Smartcard (ISO7816-3) mode ................485 19.3.13. ModBus communication ..................487 19.3.14. Receive FIFO ...................... 487 19.3.15. Wakeup from Deep-sleep mode ................488 19.3.16. USART interrupts ....................488 Register definition ....................491 19.4. 19.4.1. Control register 0 (USART_CTL0)................491 19.4.2.
Page 13 GD32E502xx User Manual 20.4.5. Timing register (I2C_TIMING) ................542 20.4.6. Timeout register (I2C_TIMEOUT) ................543 20.4.7. Status register (I2C_STAT) ..................544 20.4.8. Status clear register (I2C_STATC) ................547 20.4.9. PEC register (I2C_PEC)..................548 20.4.10. Receive data register (I2C_RDATA) ................ 548 20.4.11.
Page 14 GD32E502xx User Manual Comparator (CMP) ....................592 22.1. Overview ......................592 22.2. Characteristic...................... 592 22.3. Function overview ....................592 22.3.1. CMP inputs and outputs ..................593 22.3.2. CMP output blanking .................... 593 22.3.3. CMP register write protection ................. 594 22.3.4. CMP power mode ....................594 22.3.5.
Page 15 GD32E502xx User Manual 23.5.12. Receive FIFO identifier filter matching number register (CAN_RFIFOIFMN) ....653 23.5.13. Bit timing register (CAN_BT) .................. 654 23.5.14. Receive FIFO/mailbox private filter x register (CAN_RFIFOMPFx)(x=0..31) ....655 23.5.15. Pretended Networking mode control register 0 (CAN_PN_CTL0)......... 655 23.5.16.
Page 16: List Of Figures
GD32E502xx User Manual List of Figures ® -M33 processor ..............26 Figure 1-1. The structure of the Cortex Figure 1-2. Series system architecture of GD32E502xx series ............28 Figure 1-3. ECC decoder ........................... 33 Figure 2-1. Process of page erase operation ................... 58 Figure 2-2.
Page 17 GD32E502xx User Manual Figure 14-9. 20-bit to 16-bit result truncation..................278 Figure 14-10. Numerical example with 5-bits shift and rounding ..........279 Figure 14-11. ADC sync block diagram ....................280 Figure 14-12. Routine parallel mode on 16 channels .................281 Figure 14-13. Routine follow-up fast mode on 1 channel in continuous operation mode .282 Figure 14-14.
Page 18 GD32E502xx User Manual Figure 18-28. Channel output complementary PWM with dead-time insertion.......352 Figure 18-29. Break function diagram .......................353 Figure 18-30. Output behavior of the channel in response to a break (the break high active) ...................................354 Figure 18-31. Counter behavior with CI0FE0 polarity non-inverted in mode 2 .......355 Figure 18-32.
Page 19 GD32E502xx User Manual Figure 19-6. Configuration step when using DMA for USART reception........479 Figure 19-7. Hardware flow control between two USARTs ..............479 Figure 19-8. Hardware flow control ......................480 Figure 19-9. Break frame occurs during idle state ................482 Figure 19-10. Break frame occurs during a frame ................482 Figure 19-11.
Page 20 GD32E502xx User Manual Figure 21-8. Timing diagram of TI master mode with discontinuous transfe r ......558 Figure 21-9. Timing diagram of TI master mode with continuous transfer.......559 Figure 21-10. Timing diagram of TI slave mode..................559 Figure 21-11. Timing diagram of NSS pulse with continuous transmit........560 Figure 21-12.
Page 21 GD32E502xx User Manual CHLEN=0, CKPL=0) ..........................572 Figure 21-44. PCM standard long frame synchronization mode timing diagram (DTLEN=00, CHLEN=0, CKPL=1) ..........................572 Figure 21-45. PCM standard long frame synchronization mode timing diagram (DTLEN=10, CHLEN=1, CKPL=0) ..........................573 Figure 21-46. PCM standard long frame synchronization mode timing diagram (DTLEN=10, CHLEN=1, CKPL=1) ..........................573 Figure 21-47.
Page 22: List Of Tables
GD32E502xx User Manual List of Tables Table 1-1. Bus Interconnection Matrix......................26 Table 1-2. Memory map of GD32E502xx devices ................... 29 Table 1-3. Boot modes ............................34 Table 2-1. Base address and size for 384 KB flash memory ............. 51 Table 2-2.
Page 23 GD32E502xx User Manual Table 14-1. ADC internal input signals .....................269 Table 14-2. ADC input pins definition......................269 Table 14-3. External trigger source for ADC0 and ADC1 ..............276 Table 14-4. t timings depending on resolution ................277 CONV Table 14-5. Maximum output results for N and M combimations (grayed values indicates truncation) ..............................279 Table 14-6.
Page 24 GD32E502xx User Manual Table 23-7. Mailbox arbitration value(32 bit) when local priority disabled .......616 Table 23-8. Mailbox arbitration value(35 bit) when local priority enabled.........617 Table 23-9. Rx mailbox matching ........................623 Table 23-10. Rx FIFO matching ........................624 Table 23-11. Interrupt events.........................637 Table 23-12.
Page 25: System And Memory Architecture
GD32E502xx User Manual System and memory architecture ® The GD32E502xx series are 32-bit general-purpose microcontrollers based on the Arm Cortex ® -M33 processor. The Arm ® Cortex ® -M33 processor includes two AHB buses known as ® ® Code and System buses. All memory accesses of the Arm Cortex -M33 processor are executed on these two buses according to the different purposes and the target memory...
Page 26: System Architecture
GD32E502xx User Manual ® Figure 1-1. The structure of the Cortex -M33 processor Cortex-M33 processor Cortex-M33 core Nested Interrupts Vectored Floating Point Interrupt Unit(FPU) Controller (NVIC) DSP Extension Data Breakpoint Memory Watchpoint Unit Protection And Trace (BPU) Unit(MPU) (DWT) Serial-Wire Or JTAG Instrumentation Trace Port...
Page 27 GD32E502xx User Manual CBUS SBUS DMA0 DMA1 AHB1 AHB2 As is shown above, there are several masters connected with the AHB interconnect matrix, including CBUS, SBUS, DMA0 and DMA1. CBUS is the code bus of the Cortex® -M33 core, which is used for any instruction fetch and data access to the Code region. Similarly, SBUS is the system bus of the Cortex®-M33 core, which is used for instruction/vector fetches, data loading/storing and debugging access of the system regions.
Page 28: Memory Map
GD32E502xx User Manual Figure 1-2. Series system architecture of GD32E502xx series 1.1V TPIU GPIO Ports CBus A, B, C, D,E, AHB2: Fma x = 100MHz POR/PDR ARM Cortex-M33 Processor C/SBus SRAM : 100MHz SRAM Controller SBus Flash CBus Flash Memory Memory NVIC Controller...
Page 29: Table 1-2. Memory Map Of Gd32E502Xx Devices
GD32E502xx User Manual ® Additionally, a pre-defined memory map is provided by the Cortex -M33 processor to reduce the software complexity of repeated implementation of different device vendors. In the map, ® ® some regions are used by the Arm Cortex -M33 system peripherals which can not be modified.
Page 30 GD32E502xx User Manual Pre-defined Address Peripherals Regions 0x4001 8400 - 0x4001 87FF TRIGSEL 0x4001 8000 - 0x4001 83FF Reserved 0x4001 7C00 - 0x4001 7FFF 0x4001 5800 - 0x4001 7BFF Reserved 0x4001 5400 - 0x4001 57FF TIMER20 0x4001 5000 - 0x4001 53FF TIMER19 0x4001 4C00 - 0x4001 4FFF Reserved...
Page 31 GD32E502xx User Manual Pre-defined Address Peripherals Regions 0x4000 7000 - 0x4000 73FF 0x4000 6C00 - 0x4000 6FFF 0x4000 6800 - 0x4000 6BFF Reserved 0x4000 6400 - 0x4000 67FF Reserved 0x4000 6000 - 0x4000 63FF Reserved 0x4000 5C00 - 0x4000 5FFF Reserved 0x4000 5800 - 0x4000 5BFF I2C1...
Page 32: On-Chip Sram Memory
GD32E502xx User Manual Pre-defined Address Peripherals Regions 0x1FFF 7400 - 0x1FFF AFFF Reserved 0x1FFF 7000 - 0x1FFF 73FF OTP(1KB) 0x0A00 D000 - 0x1FFF 6FFF Reserved 0x0A00 C000 - 0x0A00 CFFF Shared SRAM(4KB) 0x0A00 8000 - 0x0A00 BFFF 0x0A00 6000 - 0x0A00 7FFF SRAM(48KB) 0x0A00 4000 - 0x0A00 5FFF 0x0A00 0000 - 0x0A00 3FFF...
Page 33: Figure 1-3. Ecc Decoder
GD32E502xx User Manual Decoder: When performing a SRAM read operation, it uses the same algorithm as the encoder to decode and generate a 7-bit ECC code. The ECC code includes ECC error status and information which specific bit of the 32-bit data has single bit error. The decoder is shown in the figure Figure 1-3.
Page 34: On-Chip Flash Memory
GD32E502xx User Manual non-correction event is detected, a NMI interrupt will be generated. On-chip Flash memory 1.3.2. The devices provide high-density on-chip flash memory, which is structured as follows: Up to 384KB of main Flash memory.   Up to 18KB of information blocks for the boot loader. ...
Page 35: System Configuration Controller
GD32E502xx User Manual 1.5. System configuration controller The main purposes of the system configuration controller (SYSCFG) are the following:  Remapping of some I/O ports Managing the external interrupt line connection to the GPIOs ...
Page 36: System Configuration Registers
GD32E502xx User Manual 1.6. System configuration registers SYSCFG base address: 0x4001 0000 System configuration register 0 (SYSCFG_CFG0) 1.6.1. Address offset: 0x00 Reset value: 0x0000 000X (X indicates BOOT_MODE[1:0] may be any value according to the BOOT0 pin and the BOOT1_n pin after reset.) This register can be accessed by word(32-bit).
Page 37: System Configuration Register 1 (Syscfg_Cfg1)
GD32E502xx User Manual System configuration register 1 (SYSCFG_CFG1) 1.6.2. Address offset: 0x04 Reset value: 0x0000 0000 This register can be accessed by word(32-bit). ADC0CH ADC0CH ADC1CH ADC1CH Reserved 9RMP 8RMP 15RMP 14RMP Reserved Bits Fields Descriptions ADC0CH9RMP ADC0 channel 9 remapping bit 0: ADC0_IN9 is mapping on PB1.
Page 38: Exti Sources Selection Register 1 (Syscfg_Extiss1)
GD32E502xx User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:12 EXTI3_SS[3:0] EXTI 3 sources selection X000: PA3 pin X001: PB3 pin X010: PC3 pin X011: PD3 pin X100: PE3 pin X101: PF3 pin X110: reserved X111: reserved 11:8 EXTI2_SS[3:0]...
Page 39 GD32E502xx User Manual Reset value: 0x0000 0000 This register can be accessed by word(32-bit). Reserved EXTI7_SS [3:0] EXTI6_SS [3:0] EXTI5_SS [3:0] EXTI4_SS [3:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:12 EXTI7_SS[3:0] EXTI 7 sources selection X000: PA7 pin X001: PB7 pin X010: PC7 pin...
Page 40: Exti Sources Selection Register 2 (Syscfg_Extiss2)
GD32E502xx User Manual X010: PC4 pin X011: PD4 pin X100: PE4 pin X101: PF4 pin X110: reserved X111: reserved EXTI sources selection register 2 (SYSCFG_EXTISS2) 1.6.5. Address offset: 0x10 Reset value: 0x0000 0000 This register can be accessed by word(32-bit). Reserved EXTI11_SS [3:0] EXTI10_SS [3:0]...
Page 41: Exti Sources Selection Register 3 (Syscfg_Extiss3)
GD32E502xx User Manual X001: PB9 pin X010: PC9 pin X011: PD9 pin X100: PE9 pin X101: reserved X110: reserved X111: reserved EXTI8_SS[3:0] EXTI 8 sources selection X000: PA8 pin X001: PB8 pin X010: PC8 pin X011: PD8 pin X100: PE8 pin X101: reserved X110: reserved X111: reserved...
Page 42: System Configuration Register 2 (Syscfg_Cfg2)
GD32E502xx User Manual X000: PA14 pin X001: PB14 pin X010: PC14 pin X011: PD14 pin X100: PE14 pin X101: reserved X110: reserved X111: reserved EXTI13_SS[3:0] EXTI 13 sources selection X000: PA13 pin X001: PB13 pin X010: PC13 pin X011: PD13 pin X100: PE13 pin X101: reserved X110: reserved...
Page 43: System Status Register (Syscfg_Stat)
GD32E502xx User Manual Bits Fields Descriptions 31:3 Reserved Must be kept at reset value. LVD_LOCK LVD lock This bit is set by softw are and cleared by a system reset. 0: The LVD interrupt is disconnected from the break input of TIMER0/7/19/20. LVDE and LVDT[2:0] in the PMU_CTL register can be programmed.
Page 44: System Configuration Register 3 (Syscfg_Cfg3)
GD32E502xx User Manual The softw are can clear it by w riting 1. 0: no HXTAL clock moniotor error 1: HXTAL clock moniotor is detected. FLASHECCIF Flash ECC NMI interrupt flag The softw are can clear it by w riting 1. 0: no Flash ECC error 1: Flash ECC error is detected.
Page 45: Timer Input Source Select Register (Syscfg_Timerinsel)
GD32E502xx User Manual 11:5 Reserved Must be kept at reset value. NMIPINIE NMI pin interrupt enable 0: disable 1: enable CKMNMIIE HXTAL clock moniotor NMI interrupt enable 0: disable 1: enable FLASHECCIE Flash ECC NMI enable 0: disable 1: enable SRAMECCSEIE SRAM single bit correction error interrupt enable 0: SRAM single bit correction error interrupt is disabled.
Page 46 GD32E502xx User Manual 29:28 TIMER7_ETI_SEL[1: TIMER7 external trigger select 00: timer external trigger 0 01: timer external trigger 1 10: timer external trigger 2 11: Reserved 27:26 Reserved Must be kept at reset value. 25:24 TIMER19_ETI_SEL[1 TIMER19 external trigger select 00: timer external trigger 0 01: timer external trigger 1 10: timer external trigger 2...
Page 47: Device Electronic Signature
GD32E502xx User Manual 0: from GPIO pin 1: from TRIGSEL 13:10 Reserved Must be kept at reset value. TIMER19_BRKIN0_S TIMER19 break input 0 select 0: from GPIO pin 1: from TRIGSEL TIMER19_BRKIN1_S TIMER19 break input 1 select 0: from GPIO pin 1: from TRIGSEL TIMER19_BRKIN2_S TIMER19 break input 0 select...
Page 48: Memory Density Information
GD32E502xx User Manual Memory density information 1.7.1. Base address: 0x1FFF F7E0 The value is factory programmed and can never be altered by user. This register has to be accessed by word(32-bit). SRAM_DENSITY[15:0] FLASH_DENSITY[15:0] Bits Fields Descriptions 31:16 SRAM_DENSITY SRAM density [15:0] The value indicates the on-chip SRAM density of the device in Kbytes.
Page 49 GD32E502xx User Manual UNIQUE_ID[47:32] Bits Fields Descriptions 31:0 UNIQUE_ID[63:32] Unique device ID Base address: 0x1FFF F7F0 The value is factory programmed and can never be altered by user. This register has to be accessed by word(32-bit). UNIQUE_ID[95:80] UNIQUE_ID[79:64] Bits Fields Descriptions 31:0 UNIQUE_ID[95:64]...
Page 50: Flash Memory Controller (Fmc)
GD32E502xx User Manual Flash memory controller (FMC) 2.1. Overview The flash memory controller, FMC, provides all the necessary functions for the on-chip flash memory. A little waiting time is needed while CPU executes instructions stored from the 384K bytes of the flash. It also provides page erase, mass erase, and program operations for flash memory.
Page 51: Table 2-1. Base Address And Size For 384 Kb Flash Memory
GD32E502xx User Manual erased individually. Table 2-1. Base address and size for 384 KB flash memory shows the base address and size. Table 2-1. Base address and size for 384 KB flash memory Block Nam e Address size(bytes) Page 0 0x0800 0000 - 0x0800 03FF Page 1 0x0800 0400 - 0x0800 07FF...
Page 52: Table 2-3. Base Address And Size For 128Kb Flash Memory
GD32E502xx User Manual Block Nam e Address size(bytes) Page 1 0x0800 0400 - 0x0800 07FF Page 2 0x0800 0800 - 0x0800 0BFF Page 255 0x0803 FC00 - 0x0803 FFFF Data Flash 0x0880 0000 - 0x0880 FFFF Extend Flash Block 64KB EEPROM backup EEPROM...
Page 53: Table 2-4. 64Kb Flash Base Address And Size For Flash Memory
GD32E502xx User Manual Block Nam e Address size(bytes) map of GD32E502xx devices. Information Block Bootloader 0x1FFF B000 - 0x1FFF F7FF 18KB Option bytes 0 0x1FFF F800 - 0x1FFF F817 Option byte Block Option bytes 1 0x4002 2068 One-time program Block OTP bytes 0x1FFF 7000~0x1FFF 73FF 1.
Page 54: Error Checking And Correcting (Ecc)
GD32E502xx User Manual only once. If any bit has been set 0, the entire double word cannot be written anymore, even with the value 0x0000 0000 0000 0000. Error Checking and Correcting (ECC) 2.3.2. The ECC mechanism supports:  One error detection and correction ...
Page 55: Read Operations
GD32E502xx User Manual When an ECC error is reported, a new read at the error address may not generate an ECC error if the data is still present in the current buffer / prefetch buffer / cache, even if ECCCOR and ECCDET are cleared.
Page 56: Dual Bank Architecture With Read-While-Write (Rww) Capability
GD32E502xx User Manual operation. So in the case of sequential code, the next data can get from current buffer without repeat fetch from flash memory. Pre-fetch buffer: The pre-fetch buffer is enabled by setting the PFEN bit in the FMC_WS register. In the case of sequential code, when CPU executes the current buffer data (64-bit), 32-bit needs at least 2 clocks and 16-bit needs at least 4 clocks.
Page 57: Page Erase
GD32E502xx User Manual The unlocking sequence includes two write operations, which are writing 0x45670123 and 0xCDEF89AB to FMC_OBKEY register, then the OBWEN bit in FMC_CTL1 register is set by hardware. The software can clear OBWEN bit to protect the OB0PG bit and OB0ER bit in FMC_CTL1 register again.
Page 58: Mass Erase
GD32E502xx User Manual Figure 2-1. Process of page erase operation Start Is the LK bit 0 Unlock the FMC_CTLx Is the BUSY bit 0 Set the FMC_ADDRx, PER bit Send the command to FMC by setting START Is the BUSY bit 0 Finish Mass erase 2.3.7.
Page 59: Main Flash Programming
GD32E502xx User Manual Since all flash data will be reset to a value of 0xFFFF FFFF, the mass erase operation can be implemented using a program that runs in SRAM or by using the debugging tool to access the FMC registers directly. Additionally, the mass erase operation will be ignored if any page is erase / program protected.
Page 60 GD32E502xx User Manual  Unlock the FMC_CTLx register if necessary.  Check the BUSY bit in FMC_STATx register to confirm that no flash memory operation is in progress (BUSY equal to 0). Otherwise, wait until the operation has been finished. ...
Page 61: Main Flash Fast Programming
GD32E502xx User Manual Figure 2-3. Process of word program operation Start Is the LK bit 0 Unlock the FMC_CTLx Is the BUSY bit 0 Set the PG bit Perform word write by DBUS Is the BUSY bit 0 Finish Note: Reading the flash should be avoided when a program / erase operation is ongoing in the same bank.
Page 62: Figure 2-4. Process Of Fa St Programming Operation
GD32E502xx User Manual  1. Set Shared RAM to fast program mode by configuring the SRAMCMD bits to "01".  2. Check the row (32 double-word) in flash to confirm all data in flash is all 0xFF. The check blank command can be used to check the page the row in. ...
Page 63 GD32E502xx User Manual Figure 2-4. Process of fast programming operation Start Configure SRAMCMD Check the row is all 0xFF Unlock the Is the LK bit is 0 FMC_CTLx Is the BUSY bit is 0 Set the FSTPG bit Perform 32 double words write by DBUS Set the START bit Is the BUSY bit is 0...
Page 64: Check Blank Command
GD32E502xx User Manual 5. The cache must be flushed before fast programming. Check blank command 2.3.10. The check blank command is used to check if the flash area which is specified by FMC_ADDRx and CBCMDLEN bits in FMC_CTLx register are all 0xFF or not. Configure the check blank command by setting the CBCMD bit in FMC_CTLx register and send the check blank command to the FMC by setting the START bit in FMC_CTLx register, the BUSY bit will be set, and the hardware will check if the flash area are all 0xFF or not.
Page 65: Data Flash Operation
GD32E502xx User Manual SRAMCMD will be cleared. Otherwise, wait until the command has been finished. Note that bank 1 is used in the process and cannot be used for other operations. Fast program SRAM The fast program SRAM command is sent by configuring the SRAMCMD bits as "01". After sending the fast program SRAM command, the Shared RAM initializes to all 1.
Page 66: Emulated Eeprom
GD32E502xx User Manual Programming. Emulated EEPROM 2.3.14. The EEPROM SRAM size is configured by EPSIZE. And the EEPROM backup size is configured by EFALC. The larger the ratio of EEPROM backup and EEPROM SRAM makes the better endurance. The emulated EEPROM file system locates all valid EEPROM SRAM data records in EEPROM backup and copies the newest data to Shared RAM.
Page 67: Option Bytes 0 Erase
GD32E502xx User Manual Option bytes 0 erase 2.3.15. The FMC provides an erase function which is used to initialize the option bytes 0 block in flash. The following steps show the erase sequence.  Unlock the FMC_CTL1 register if necessary. ...
Page 68: Option Bytes Description
GD32E502xx User Manual Option bytes 1 programming The following steps show the modify operation sequence.  Unlock the FMC_CTL1 register if necessary.  Check the BUSY bit in FMC_STAT1 register to confirm that no flash memory operation is in progress (BUSY equal to 0). Otherwise, wait until the operation has been finished. ...
Page 69: Table 2-6. Option Bytes 0
GD32E502xx User Manual Table 2-6. Option bytes 0 Address Nam e Description option bytes 0 security protection value 0xA5 : no security protection 0x1fff f800 OB_SPC any value except 0xA5 or 0xCC : protection level low 0xCC : protection level high 0x1fff f801 OB_SPC_N OB_SPC complement value...
Page 70: Table 2-7. Option Bytes 1 (384K Flash Or 256K Flash)
GD32E502xx User Manual Address Nam e Description 0x1fff f80d OB_BK0WP_N[23:16] OB_BK0WP complement value bit 23 to 16 0x1fff f80e OB_BK0WP[31:24] Page erase / program protection of bank0 bit 31 to 24 0x1fff f80f OB_BK0WP_N[31:24] OB_BK0WP complement value bit 31 to 24 0x1fff f810 OB_BK1WP[7:0] Page erase / program protection of bank1 bit 7 to 0...
Page 71: Table 2-8. Option Bytes 1 (128K Flash)
GD32E502xx User Manual Address Nam e Description 1011: Reserved 1100: Reserved 1101: Reserved 1110: Reserved 1111: 0 Bytes Specified the size of the data flash and EEPROM backup in the extend flash memory. Extend memory that is not partitioned for data flash is used to store EEPROM records.
Page 72: Table 2-9. Option Bytes 1 (64K Fla Sh)
GD32E502xx User Manual Address Nam e Description 1010: Reserved 1011: Reserved 1100: Reserved 1101: Reserved 1110: Reserved 1111: 0 Bytes Specified the size of the data flash and EEPROM backup in the extend flash memory. Extend memory that is not partitioned for data flash is used to store EEPROM records.
Page 73: Erase / Program Protection
GD32E502xx User Manual Address Nam e Description 1001: Reserved 1010: Reserved 1011: Reserved 1100: Reserved 1101: Reserved 1110: Reserved 1111: 0 Bytes Specified the size of the data flash and EEPROM backup in the extend flash memory. Extend memory that is not partitioned for data flash is used to store EEPROM records.
Page 74: Table 2-10. Ob_Bk0Wp Bit For Pages Protected
GD32E502xx User Manual get the attention of the CPU. Page erase / program protection of bank 0 The page erase / program protection of bank 0 can be individually enabled by configuring the OB_BK0WP[31:0] bit field to 0 in the option bytes 0. If a page erase operation is executed on the Option Byte region, all the flash memory page erase / program protection functions will be disabled.
Page 75: Table 2-12. Ob_Dfwp Bit For Pages Protected (Efalc: Except 0X3 / 0Xc / 0Xe)
GD32E502xx User Manual Note: 1. BANK1_SIZE is the memory size of bank1. 2. OTP write protection is controlled by OB_BK1WP[7]. Page erase / program protection of data flash The page erase / program protection of data flash can be individually enabled by configuring the OB_DFWP[7:0] bit field to 0 in the option bytes 0.
Page 76: Security Protection
GD32E502xx User Manual for protected shows which pages are protected by setting OB_EPWP[7:0]. Table 2-14. OB_EPWP bit for protected OB_EPWP bit pages protected OB_EPWP[0] EEPROM_SIZ E / 8 OB_EPWP[1] EEPROM_SIZ E / 8 OB_EPWP[6] EEPROM_SIZ E / 8 OB_EPWP[7] EEPROM_SIZ E / 8 Note: EEPROM_SIZE is the memory size of backup EEPROM.
Page 77: Table 2-15. Pgserr Conditions
GD32E502xx User Manual PGSERR conditions. Table 2-15. PGSERR conditions Mode Condition Operation program / fast PG and FSTPG are cleared Write data program 1. not w rite by address order fast program 2. not w rite from 0 or not w rite full 32 double-w ord Set START 3.
Page 78: Table 2-16. Pgaerr Conditions
GD32E502xx User Manual Table 2-16. PGAERR bit in FMC_CTLx register will be set if one of the conditions occurs in PGAERR conditions. Table 2-16. PGAERR conditions Mode Condition Operation 1. The DBUS program do not use 32-bit w rite. 2. The DBUS w rite is not alignment. The first DBUS program Write data w rite must double-w ord alignment and the second...
Page 79: Register Definition
GD32E502xx User Manual 2.4. Register definition FMC base address: 0x4002 2000 Wait state register (FMC_WS) 2.4.1. Address offset: 0x00 Reset value: 0x0000 0210 This register has to be accessed by word (32-bit). PRAMRD BRAMRD ERAMRD Reserved SLEEP_S Reserved Reserved IDRST Reserved IDCEN Reserved...
Page 80: Ecc Control And Status Register (Fmc_Ecccs)
GD32E502xx User Manual 1: Reset the cache if cache is disabled Reserved Must be kept at reset value. IDCEN Cache enable 0: Cache disable 1: Cache enable Reserved Must be kept at reset value. PFEN Pre-fetch enable 0: Pre-fetch disable 1: Pre-fetch enable Reserved Must be kept at reset value.
Page 81 GD32E502xx User Manual 0: No ECC error is detected and corrected. 1: An ECC error is detected and corrected. EPECCDET EEPROM tw o bit errors detect flag. This bit is cleared by w riting 1. 0: Tw o ECC errors of EEPROM are not detected. 1: Tw o ECC errors of EEPROM are detected.
Page 82: Unlock Key Register 0 (Fmc_Key0)
GD32E502xx User Manual OB0_ECC If an ECC bit error is detected in option bytes 0, this bit w ill be set. And the ECCADDR records the offset address of option bytes 0. 0: No ECC error is detected in option bytes 0. 1: An ECC bit error is detected in option bytes 0.
Page 83: Control Register 0 (Fmc_Ctl0)
GD32E502xx User Manual 31:16 Reserved Must be kept at reset value. RSTERR If the voltage is below 3.0V or a system reset occurs during flash programming or erasing, an error w ill be generated and this bit w ill be set. When the error is occurred, the data in the current address unreliable, and it is necessary to erase and program again.
Page 84 GD32E502xx User Manual Reserved ENDIE Reserved ERRIE Reserved FSTPG START Reserved Bits Fields Descriptions 31:29 CBCMDLEN[2:0] CBCMD read length 2^(CBCMDLEN). The read length by check blank command. The read length is 2^ CBCMDLEN double w ords. 28:17 Reserved Must be kept at reset value. CBCMD The command to check the selected area is blank or not.
Page 85: Address Register 0 (Fmc_Addr0)
GD32E502xx User Manual 1: main flash page erase command Main flash program command bit This bit is set or clear by softw are 0: no effect 1: main flash program command Note: This register should be reset after the corresponding flash operation completed. Address register 0 (FMC_ADDR0) 2.4.6.
Page 86: Unlock Key Register 1 (Fmc_Key1)
GD32E502xx User Manual Unlock key register 1 (FMC_KEY1) 2.4.8. Address offset: 0x48 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). KEY[31:16] KEY[15:0] Bits Fields Descriptions 31:0 KEY[31:0] FMC_CTL1 unlock key These bits are only be w ritten by softw are Write KEY[31:0] w ith key to unlock FMC_CTL1 register.
Page 87: Control Register 1 (Fmc_Ctl1)
GD32E502xx User Manual 0: The checked page is all 0xFF. 1: The checked page is not all 0xFF. ENDF End of operation flag bit When the operation executed successfully, this bit is set by hardw are. The softw are can clear it by w riting 1. WPERR Erase / Program protection error flag bit When erase / program on protected pages, this bit is set by hardw are.
Page 88 GD32E502xx User Manual 01: set fast program RAM mode 10: set Basic RAM mode 11: set EEPROM RAM mode 23:17 Reserved Must be kept at reset value. CBCMD The command to check the selected page is blank or not. 15:14 Reserved Must be kept at reset value.
Page 89: Address Register 1 (Fmc_Addr1)
GD32E502xx User Manual This bit is set or clear by softw are 0: no effect 1: option bytes 0 program command MERDF Data flash mass erase command bit This bit is set or cleared by softw are 0: no effect 1: Data flash mass erase command Main flash mass erase command bit This bit is set or cleared by softw are...
Page 90: Option Byte Status Register (Fmc_Obstat)
GD32E502xx User Manual Reset value: 0x0000 0000 (When the EEPROM has been configured as valid space by EPSIZE and EFALC in option byets 1, the reset value is 0x0000 0000. Otherwise, the reset value is 0x0FFF FFFF.) This register has to be accessed by word (32-bit). EPCNT[31:16] EPCNT[15:0] Bits...
Page 91: Erase / Program Protection Register 0 (Fmc_Wp0)
GD32E502xx User Manual Erase / Program protection register 0 (FMC_WP0) 2.4.14. Address offset: 0x60 Reset value: 0xXXXX XXXX This register has to be accessed by word(32-bit). BK0WP[31:16] BK0WP[15:0] Bits Fields Descriptions 31:0 BK0WP[31:0] Store OB_BK0WP[31:0] of option bytes 0 block after system reset. Erase / Program protection register 1 (FMC_WP1) 2.4.15.
Page 92: Product Id Register (Fmc_Pid)
GD32E502xx User Manual OB1STA EPLOAD Reserved EPSIZE[3:0] EFALC[3:0] Reserved OB1LK OB1ERR Bits Fields Descriptions 31:16 LKVAL[15:0] Load LKVAL of option byte 1 after reset. These bits can be w ritten by softw are when OB1LK is 0. EPLOAD Load EPLOAD of option byte 1 after reset. This bit can be w ritten by softw are when OB1LK is 0.
Page 93 GD32E502xx User Manual These bits are read only by softw are. These bits are unchanged constant after pow er on. These bits are one time program w hen the chip produced.
Page 94: Power Management Unit (Pmu)
GD32E502xx User Manual Power management unit (PMU) Overview 3.1. The power consumption is regarded as one of the most important issues for the devices of GD32E502xx series. Power management unit (PMU) provides three types of power saving modes, including Sleep, Deep-sleep and Standby mode. These modes reduce the power consumption and allow the application to achieve a best tradeoff among the conflicting demands of CPU operating time, speed and power consumption.
Page 95: Backup Domain
GD32E502xx User Manual Figure 3-1. Power supply overview Backup Domain 3.3V/5V LXTAL BPOR Domain WKUPx WKUPR BREG PC13 BKP PAD WKUPN NRST WKUPF SLEEPING Cortex-M33 FWDGT SLEEPDEEP HXTAL POR / PDR AHB IPs APB IPs 1.1V 1.1V Domain Domain 3.3V/5V IRC8M IRC40K PLLs...
Page 96: Vdd / Vdda Power Domain
GD32E502xx User Manual  PC13 can be used as GPIO or RTC function pin described in the RTC clock calibration.  PC14 and PC15 can be used as either GPIO or LXTAL crystal oscillator pins. power domain 3.3.2. domain includes two parts: V domain and V domain.
Page 97: Figure 3-3. Waveform Of The Bor
GD32E502xx User Manual shows the relationship between the supply voltage and the BOR reset signal. V which defined in the BOR_TH bits in option bytes, indicates the threshold of BOR on reset. The hysteresis voltage (V ) is 40mV. hyst Figure 3-3.
Page 98: Figure 3-4. Waveform Of The Lvd Threshold
GD32E502xx User Manual Figure 3-4. Waveform of the LVD threshold threshold 100mV hyst LVD output Figure 3-5. Waveform of the OVD threshold threshold 25mV hyst OVD output Generally, digital circuits are powered by V , while most of analog circuits are powered by .
Page 99: 1.1V Power Domain
GD32E502xx User Manual The V pin is only available on 100-pin and 64-pin packages. For other packages, the V REF+ REF+ pin is not available and it is internally connected to V . The V pin is internally connected REF- to V 1.1V power domain 3.3.3.
Page 100 GD32E502xx User Manual and SRAM2 (32kB ~ 48kB) in deep sleep mode can be set respectively. The LDO can operate in normal mode or in low power mode depending on the LDOLP bit in the PMU_CTL register. Before entering the Deep-sleep mode, it is necessary to set the SLEEPDEEP bit in the ®...
Page 101: Table 3-1. Power Saving Mode Summary
GD32E502xx User Manual alarm, the FWDGT reset and the rising edge on WKUP pin. The Standby mode achieves the lowest power consumption, but spends longest time to wake up. Besides, the contents of SRAM and registers in 1.1V power domain are lost in Standby mode. When exiting from the ®...
Page 102: Register Definition
GD32E502xx User Manual Register definition 3.4. PMU base address: 0x4000 7000 Control register (PMU_CTL) 3.4.1. Address offset: 0x00 Reset value: 0x0000 8000 (reset after wakeup from Standby mode) This register can be accessed by half-word(16-bit) or word(32-bit). SRAMSW SRAMSW Reserved Reserved LDEN Reserved...
Page 103: Control And Status Register (Pmu_Cs)
GD32E502xx User Manual 0: Disable w rite access to the registers in Backup domain 1: Enable w rite access to the registers in Backup domain After reset, any w rite access to the registers in Backup domain is ignored. This bit has to be set to enable w rite access to these registers.
Page 104 GD32E502xx User Manual This register can be accessed by half-word(16-bit) or word(32-bit). Reserved Reserved WUPEN1 WUPEN0 Reserved OVDF LVDF STBF Bits Fields Descriptions 31:10 Reserved Must be kept at reset value. WUPEN1 WKUP Pin1 Enable (PC13) 0: Disable WKUP pin1 function 1: Enable WKUP pin1 function If WUPEN1 is set before entering the Standby mode, a rising edge on the WKUP pin1 w ill w ake up the system from the Standby mode.
Page 105 GD32E502xx User Manual This bit is cleared only by a POR/PDR or by setting the STBRST bit in the PMU_CTL register. Wakeup Flag 0: No w akeup event has been received 1: Wakeup event occurred from the WKUP pin or the RTC alarm event This bit is reset by the system or cleared by setting the WURST bit in the PMU_CTL register.
Page 106: Backup Registers (Bkp)
GD32E502xx User Manual Backup registers (BKP) Overview 4.1. The Backup registers are located in the Backup domain that remains powered-on by V power, there are ten 16-bit (20 bytes) registers for data protection of user application data, and the wake-up action from standby mode or system reset do not affect these registers. In addition, the BKP registers can be used to implement the tamper detection and RTC calibration function.
Page 107 GD32E502xx User Manual the BKP_TPCTL register. To prevent the tamper event from losing, the edge detection is logically ANDed with the TPEN bit, used for tamper detection signal. So the tamper detection configuration should be set before enable TAMPER pin. When the tamper event is detected, the corresponding TEF bit in the BKP_TPCS register will be set.
Page 108: Register Definition
GD32E502xx User Manual Register definition 4.4. BKP base address: 0x4000 6C00 Backup data register x (BKP_DATAx) (x= 0..9) 4.4.1. Address offset: 0x04 to 0x28 Reset value: 0x0000 0000 This register can be accessed by half-word (16-bit) or word (32-bit). Reserved DATA [15:0] Bits Fields...
Page 109: Tamper Pin Control Register (Bkp_Tpctl)
GD32E502xx User Manual This bit is reset only by a Backup domain reset. CCOSEL RTC clock output selection 0: RTC clock div 64 1: RTC clock This bit is reset only by a POR. 13:10 Reserved Must be kept at reset value. ROSEL RTC output selection 0: RTC alarm pulse is selected as the RTC output...
Page 110: Tamper Control And Status Register (Bkp_Tpcs)
GD32E502xx User Manual 31:16 Reserved Must be kept at reset value. PCSEL OSC32_IN pin select 0: PC13 is OSC32_IN pin 1: PC14 is OSC32_IN pin 14:2 Reserved Must be kept at reset value. TPAL TAMPER pin active level 0: The TAMPER pin is active high 1: The TAMPER pin is active low TPEN TAMPER detection enable...
Page 111 GD32E502xx User Manual This bit is reset only by a system reset and w ake-up from Standby mode. Tamper interrupt reset 0: No effect 1: Reset the TIF bit This bit is alw ays read as 0. Tamper event reset 0: No effect 1: Reset the TEF bit This bit is alw ays read as 0.
Page 112: Reset And Clock Unit (Rcu)
GD32E502xx User Manual Reset and clock unit (RCU) 5.1. Reset control unit (RCTL) Overview 5.1.1. GD32E502xx reset control includes the control of three kinds of reset: power reset, system reset and backup domain reset. The power on reset, known as a cold reset, resets the full system except the backup domain during a power up.
Page 113: Clock Control Unit (Cctl)
GD32E502xx User Manual  FLASH or SRAM 2-bit ECC error reset (ECC_RSTn) LVD_RSTn / LOH_RSTn / LOP_RSTn / LOCKUP_RSTn / ECC_RSTn should be enable by software. A system reset resets the processor core and peripheral IP components except for the SW- DP controller and the backup domain.
Page 114: Figure 5-2. Clock Tree
GD32E502xx User Manual which can source from the IRC8M, HXTAL or PLL. The maximum operating frequency of the system clock (CK_SYS) can be up to 100 MHz. Figure 5-2. Clock tree CK_I2S (to I2S) CK_FMC SCS[1:0] FMC enable (to FMC) (by hardware) HCLK CK_IRC8M...
Page 115: Characteristics
GD32E502xx User Manual Characteristics 5.2.2.  2 to 40 MHz High speed crystal oscillator (HXTAL)  Internal 8 MHz RC oscillator (IRC8M)  32.768 KHz Low speed crystal oscillator (LXTAL)  Internal 40 KHz RC oscillator (IRC40K)  PLL clock source can be HXTAL or IRC8M ...
Page 116: Figure 5-4. Hxtal Clock Source In Bypass Mode
GD32E502xx User Manual Figure 5-4. HXTAL clock source in bypass mode Select the HXTAL frequency scale by using the HXTALSCAL bit in the control register, RCU_CTL. If HXTAL frequency is higher than 8MHz, HXTALSCAL bit must be set. Internal 8 MHz RC Oscillator (IRC8M) The Internal 8 MHz RC oscillator, IRC8M, has a fixed frequency of 8 MHz and is the default clock source selection for the CPU when the device is powered up.
Page 117 GD32E502xx User Manual related interrupt enable bit, LXTALSTBIE, in the interrupt register RCU_INT is set when the LXTAL becomes stable. Select external clock bypass mode by setting the LXTALBPS and LXTALEN bits in the backup domain control register (RCU_BDCTL). The CK_LXTAL is equal to the external clock which drives the OSC32IN pin.
Page 118: Table 5-1. Clock Source Select
GD32E502xx User Manual in the control register, RCU_CTL. This function should be enabled after the HXTAL start-up delay and disabled when the HXTAL is stopped. Once the HXTAL failure is detected, Loss- of-HXTAL reset will generate decided by LOHRSTEN in the reset source /clock register, RCU_RSTSCK.
Page 119: Table 5-2. Core Domain Voltage Selected In Deep-Sleep Mode
GD32E502xx User Manual If the USART0/1/2 clock is selected IRC8M clock in Deep-sleep mode, they have capable of open IRC8M clock or close IRC8M clock, which used to the USART0/1/2 to wake up the Deep-sleep mode. Voltage control The core domain voltage in Deep-sleep mode can be controlled by DSLPVS[1:0] bits in the Deep-sleep mode voltage register (RCU_DSV).
Page 120: Register Definition
GD32E502xx User Manual 5.3. Register definition RCU base address: 0x4002 1000 Control register (RCU_CTL) 5.3.1. Address offset: 0x00 Reset value: 0x0000 XX83 where X is undefined. This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit) HXTALSC HXTALB HXTALST HXTALE Reserved PLLSTB PLLEN...
Page 121 GD32E502xx User Manual LCKMEN enable the hardw are detects that the LXTAL clock is stuck at a low /high state or slow dow n to about 20KHz. PLLMEN PLL clock monitor enable 0: Disable the PLL clock monitor 1: Enable the PLL clock monitor PLLMEN enable the hardw are detects that the PLL clock is stuck at a low /high state.
Page 122: Configuration Register 0 (Rcu_Cfg0)
GD32E502xx User Manual Reserved Must be kept at reset value. IRC8MSTB IRC8M high speed internal oscillator stabilization flag Set by hardw are to indicate if the IRC8M oscillator is stable and ready for use. 0: IRC8M oscillator is not stable 1: IRC8M oscillator is stable IRC8MEN Internal high speed oscillator enable...
Page 123 GD32E502xx User Manual 26:24 CKOUTSEL[2:0] CK_OUT clock source selection Set and reset by softw are. 000: No clock selected 001: Reserved 010: Internal 40K RC oscillator clock selected 011: External low speed oscillator clock selected 100: System clock selected 101: Internal 8MHz RC oscillator clock selected 110: External high speed oscillator clock selected 111: (CK_PLL / 2) or CK_PLL selected depend on PLLDV 23:22...
Page 124 GD32E502xx User Manual 11101: (PLL source clock x 30) 11110: (PLL source clock x 31) 11111: (PLL source clock x 31) Note: The PLL output frequency must not exceed 100 MHz. DPLL Double PLL clock 0: Double PLL clock 1: PLL clock PLLSEL PLL clock source selection Set and reset by softw are to control the PLL clock source.
Page 125: Interrupt Register (Rcu_Int)
GD32E502xx User Manual 01: Select CK_HXTAL as the CK_SYS source 10: Select CK_PLL as the CK_SYS source 11: Reserved SCS[1:0] System clock sw itch Set by softw are to select the CK_SYS source. Because the change of CK_SYS has inherent latency, softw are should read SCSS to confirm w hether the sw itching is complete or not.
Page 126 GD32E502xx User Manual 1: Reset LCKMIF flag PLLSTBIC PLL stabilization interrupt clear Write 1 by softw are to reset the PLLSTBIF flag. 0: Not reset PLLSTBIF flag 1: Reset PLLSTBIF flag HXTALSTBIC HXTAL stabilization interrupt clear Write 1 by softw are to reset the HXTALSTBIF flag. 0: Not reset HXTALSTBIF flag 1: Reset HXTALSTBIF flag IRC8MSTBIC...
Page 127 GD32E502xx User Manual IRC8MSTBIE IRC8M stabilization interrupt enable Set and reset by softw are to enable/disable the IRC8M stabilization interrupt 0: Disable the IRC8M stabilization interrupt 1: Enable the IRC8M stabilization interrupt LXTALSTBIE LXTAL stabilization interrupt enable LXTAL stabilization interrupt enable/disable control 0: Disable the LXTAL stabilization interrupt 1: Enable the LXTAL stabilization interrupt IRC40KSTBIE...
Page 128: Apb2 Reset Register (Rcu_Apb2Rst)
GD32E502xx User Manual Set by hardw are w hen the internal 8 MHz RC oscillator clock is stable and the IRC8MSTBIE bit is set. Reset by softw are when setting the IRC8MSTBIC bit. 0: No IRC8M stabilization interrupt generated 1: IRC8M stabilization interrupt generated LXTALSTBIF LXTAL stabilization interrupt flag Set by hardw are w hen the external 32,768 Hz crystal oscillator clock is stable and...
Page 129 GD32E502xx User Manual 29:22 Reserved Must be kept at reset value TIMER20RST TIMER20 reset This bit is set and reset by softw are. 0: No reset 1: Reset the TIMER20 TIMER19RST TIMER19 reset This bit is set and reset by softw are. 0: No reset 1: Reset the TIMER19 19:15...
Page 130: Apb1 Reset Register (Rcu_Apb1Rst)
GD32E502xx User Manual 1: Reset comparator CFGRST System configuration reset This bit is set and reset by softw are. 0: No reset 1: Reset system configuration APB1 reset register (RCU_APB1RST) 5.3.5. Address offset: 0x10 Reset value: 0x0000 0000 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit) I2C1 I2C0 USART2...
Page 131 GD32E502xx User Manual I2C0RST I2C0 reset This bit is set and reset by softw are. 0: No reset 1: Reset I2C0 20:19 Reserved Must be kept at reset value USART2RST USART2 reset This bit is set and reset by softw are. 0: No reset 1: Reset USART2 USART1RST...
Page 132: Ahb Enable Register (Rcu_Ahben)
GD32E502xx User Manual AHB enable register (RCU_AHBEN) 5.3.6. Address offset: 0x14 Reset value: 0x0000 0014 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit) Reserved PFEN PEEN PDEN PCEN PBEN PAEN Reserved MFCOME DMAMUX SRAM Reserved Reserved CRCEN Reserved DMA1EN DMA0EN SPEN SPEN...
Page 133: Apb2 Enable Register (Rcu_Apb2En)
GD32E502xx User Manual 16:15 Reserved Must be kept at reset value MFCOMEN MFCOM port A clock enable This bit is set and reset by softw are. 0: Disabled MFCOM port A clock 1: Enabled MFCOM port A clock 13:7 Reserved Must be kept at reset value CRCEN CRC clock enable...
Page 134 GD32E502xx User Manual TRIGSEL TIMER20 TIMER19E CAN1EN CAN0EN Reserved Reserved USART0 TIMER7E TIMER0E Reserved SPI0EN ADC1EN ADC0EN Reserved CMPEN CFGEN Bits Fields Descriptions CAN1EN CAN1 clock enable This bit is set and reset by softw are. 0: Disabled CAN1 clock 1: Enabled CAN1 clock CAN0EN CAN0 clock enable...
Page 135: Apb1 Enable Register (Rcu_Apb1En)
GD32E502xx User Manual 1: Enabled TIMER7 timer clock SPI0EN SPI0 clock enable This bit is set and reset by softw are. 0: Disabled SPI0 clock 1: Enabled SPI0 clock TIMER0EN TIMER0 timer clock enable This bit is set and reset by softw are. 0: Disabled TIMER0 timer clock 1: Enabled TIMER0 timer clock ADC1EN...
Page 136 GD32E502xx User Manual Bits Fields Descriptions 31:30 Reserved Must be kept at reset value DACEN DAC clock enable This bit is set and reset by softw are. 0: Disabled DAC clock 1: Enabled DAC clock PMUEN Pow er interface clock enable This bit is set and reset by softw are.
Page 137: Backup Domain Control Register (Rcu_Bdctl)
GD32E502xx User Manual 1: Enabled SPI1 clock 13:12 Reserved Must be kept at reset value WWDGTEN Window w atchdog timer clock enable This bit is set and reset by softw are. 0: Disabled w indow w atchdog timer clock 1: Enabled w indow w atchdog timer clock 10:6 Reserved Must be kept at reset value...
Page 138: Reset Source /Clock Register (Rcu_Rstsck)
GD32E502xx User Manual BKPRST Backup domain reset This bit is set and reset by softw are. 0: No reset 1: Resets backup domain RTCEN RTC clock enable This bit is set and reset by softw are. 0: Disabled RTC clock 1: Enabled RTC clock 14:10 Reserved...
Page 139 GD32E502xx User Manual Reset value: 0x0C80 0000, reset flags reset by power reset only, other reset by system reset. This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit) WWDGT FWDGT LOCKUP RSTFC Reserved RSTF RSTF RSTF RSTF RSTF RSTF RSTF RSTF RSTF...
Page 140 GD32E502xx User Manual Reset by w riting 1 to the RSTFC bit. 0: No external PIN reset generated 1: External PIN reset generated OBLRSTF Option byte loader reset flag Set by hardw are w hen an option byte loader generated. Reset by w riting 1 to the RSTFC bit.
Page 141: Ahb Reset Register (Rcu_Ahbrst)
GD32E502xx User Manual 0: No CPU Lock-Up error reset generated 1: CPU Lock-Up error reset generated BORRSTF BOR reset flag Set by hardw are w hen a BOR reset generated. Reset by w riting 1 to the RSTFC bit. 0: No BOR reset generated 1: BOR reset generated 17:15 Reserved...
Page 142 GD32E502xx User Manual Reserved PFRST PERST PDRST PCRST PBRST PARST Reserved MFCOMR DMAMUX DMA1 DMA0 Reserved Reserved CRCRST Reserved Reserved Bits Fields Descriptions 31:23 Reserved Must be kept at reset value PFRST GPIO port F reset This bit is set and reset by softw are. 0: No reset GPIO port F 1: Reset GPIO port F PERST...
Page 143: Configuration Register 1 (Rcu_Cfg1)
GD32E502xx User Manual 13:7 Reserved Must be kept at reset value CRCRST CRC reset This bit is set and reset by softw are. 0: No reset CRC module 1: Reset CRC module Reserved Must be kept at reset value DMAMUXRST DMAMUX reset This bit is set and reset by softw are.
Page 144: Configuration Register 2 (Rcu_Cfg2)
GD32E502xx User Manual 0010: Input to PLL divided by 3 0011: Input to PLL divided by 4 0100: Input to PLL divided by 5 0101: Input to PLL divided by 6 0110: Input to PLL divided by 7 0111: Input to PLL divided by 8 1000: Input to PLL divided by 9 1001: Input to PLL divided by 10 1010: Input to PLL divided by 11...
Page 145: Voltage Key Register (Rcu_Vkey)
GD32E502xx User Manual 00: CK_CAN0 select CK_HXTAL 01: CK_CAN0 select CK_PCLK2 10: CK_CAN0 select CK_PCLK2/2 11: CK_CAN0 select CK_IRC8M 11:7 Reserved Must be kept at reset value USART2SEL[1:0] CK_USART2 clock source selection This bit is set and reset by softw are. 00: CK_USART2 select CK_HXTAL 01: CK_USART2 select CK_SYS 10: CK_USART2 select CK_LXTAL...
Page 146: Deep-Sleep Mode Voltage Register (Rcu_Dsv)
GD32E502xx User Manual to the RCU_VKEY, the RCU_DSV register can be w ritten. Deep-sleep mode voltage register (RCU_DSV) 5.3.15. Offset: 0x134 Reset value: 0x0000 0003 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit) Reserved Reserved DSLPVS[1:0] Bits Fields Descriptions 31:2 Reserved...
Page 147: Interrupt / Event Controller (Exti)
GD32E502xx User Manual Interrupt / event controller (EXTI) Overview 6.1. ® Cortex -M33 integrates the Nested Vectored Interrupt Controller (NVIC) for efficient exception and interrupts processing. NVIC facilitates low-latency exception and interrupt handling and power management controls. It’s tightly coupled to the processer core. You can read the Technical Reference Manual of Cortex -M33 for more details about NVIC.
Page 148: Table 6-1. Nvic Exception Types In Cortex ® -M33
GD32E502xx User Manual ® Table 6-1. NVIC exception types in Cortex -M33 Vector Exception type Priority (a) Vector address Description num ber 0x0000_0000 Reserved Reset 0x0000_0004 Reset 0x0000_0008 Non maskable interrupt. HardFault 0x0000_000C All class of fault MemManage Programmable 0x0000_0010 Memory management Prefetch fault, memory access BusFault...
Page 149 GD32E502xx User Manual Interrupt Vector Peripheral interrupt description Vector address num ber num ber IRQ 18 ADC0 and ADC1 interrupt 0x0000_0088 IRQ 19 CAN0 Interrupt for message buffer 0x0000_008C IRQ 20 CAN0 Interrupt for Bus off / Bus off done 0x0000_0090 IRQ 21 CAN0 Interrupt for Error...
Page 150 GD32E502xx User Manual Interrupt Vector Peripheral interrupt description Vector address num ber num ber IRQ52 Reserved 0x0000_0110 IRQ53 Reserved 0x0000_0114 IRQ54 TIMER5 interrupt, DAC global interrupt 0x0000_0118 IRQ55 TIMER6 global interrupt 0x0000_011C IRQ56 DMA1 Channel 0 global interrupt 0x0000_0120 IRQ57 DMA1 Channel 1 global interrupt 0x0000_0124 IRQ58...
Page 151: External Interrupt And Event (Exti) Block Diagram
GD32E502xx User Manual External interrupt and event (EXTI) block diagram 6.4. Figure 6-1. Block diagram of EXTI Polarity Software Control Trigger EXTI Line0~24 Edge detector To NVIC Interrupt Mask Control To Wakeup Unit Event Event Mask Generate Control External Interrupt and Event function overview 6.5.
Page 152: Table 6-3. Exti Source
GD32E502xx User Manual Hardware trigger Hardware trigger may be used to detect the voltage change of external or internal signals. The software should follow these steps to use this function: Configure EXTI sources in SYSCFG module based on application requirement. Configure EXTI_RTEN and EXTI_FTEN to enable the rising or falling detection on related pins.
Page 153 GD32E502xx User Manual EXTI Line Source Num ber RTC Alarm CAN0 CAN1 CMP output USART0 Wakeup USART1 Wakeup USART2 Wakeup Over voltage...
Page 154: Register Definition
GD32E502xx User Manual 6.6. Register definition EXTI base address: 0x4001 0400 Interrupt enable register (EXTI_INTEN) 6.6.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved INTEN24 INTEN23 INTEN22 INTEN21 INTEN20 INTEN19 INTEN18 INTEN17 INTEN16 INTEN15 INTEN14 INTEN13 INTEN12 INTEN11 INTEN10 INTEN9 INTEN8 INTEN7...
Page 155: Rising Edge Trigger Enable Register (Exti_Rten)
GD32E502xx User Manual Rising edge trigger enable register (EXTI_RTEN) 6.6.3. Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved RTEN24 RTEN23 RTEN22 RTEN21 RTEN20 RTEN19 RTEN18 RTEN17 RTEN16 RTEN15 RTEN14 RTEN13 RTEN12 RTEN11 RTEN10 RTEN9 RTEN8 RTEN7...
Page 156: Pending Register (Exti_Pd)
GD32E502xx User Manual This register has to be accessed by word (32-bit). Reserved SWIEV24 SWIEV23 SWIEV22 SWIEV21 SWIEV20 SWIEV19 SWIEV18 SWIEV17 SWIEV16 SWIEV15 SWIEV14 SWIEV13 SWIEV12 SWIEV11 SWIEV10 SWIEV9 SWIEV8 SWIEV7 SWIEV6 SWIEV5 SWIEV4 SWIEV3 SWIEV2 SWIEV1 SWIEV0 Bits Fields Descriptions 31:25 Reserved...
Page 157: Trigger Selection Controller (Trigsel)
GD32E502xx User Manual Trigger selection controller (TRIGSEL) Overview 7.1. The trigger selection controller (TRIGSEL) allows software to select the trigger input signal for various peripherals. TRIGSEL provides a flexible mechanism for a peripheral to select different trigger inputs. With TRIGSEL, there are up to 4 trigger selection outputs could be selected for each peripheral.
Page 158: Internal Connect
GD32E502xx User Manual Figure 7-1. TRIGSEL main composition example Trigger Select Trigger input 0 Trigger output 3 Trigger input 1 Trigger output 2 Peripheral_x Trigger output 1 Trigger output 0 Trigger input 127 INSELx Trigger Register Internal connect 7.4. The TRIGSEL allows software to select the trigger input for peripherals. The Table 7-1.
Page 159 GD32E502xx User Manual fields bits value trigger input selection 0x10 LXTAL_TRG 0x11 TIMER1_CH0 0x12 TIMER1_CH1 0x13 TIMER1_CH2 0x14 TIMER1_CH3 0x15 TIMER1_TRGO 0x16 TIMER0_CH0 0x17 TIMER0_CH1 0x18 TIMER0_CH2 0x19 TIMER0_CH3 0x1a TIMER0_MCH0 0x1b TIMER0_MCH1 0x1c TIMER0_MCH2 0x1d TIMER0_MCH3 0x1e TIMER0_TRGO 0x1f TIMER7_CH0 0x20 TIMER7_CH1...
Page 160: Table 7-2. Trigsel Input And Output Mapping
GD32E502xx User Manual fields bits value trigger input selection 0x39 TIMER20_TRGO 0x3a TIMER5_TRGO 0x3b TIMER6_TRGO 0x3c MFCOM_TRIG0 0x3d MFCOM_TRIG1 0x3e MFCOM_TRIG2 0x3f MFCOM_TRIG3 0x40 RTC_Alarm 0x41 RTC_Second 0x42 TRIGSEL_IN12 0x43 TRIGSEL_IN13 0x44~0x7f reserved shows the connection relationship Table 7-2. TRIGSEL input and output mapping between TRIGSEL input and output.
Page 161 GD32E502xx User Manual Trigger Source Trigger select TRIGSEL Register TRIGSEL output Peripherals TIMER1_TRGO output1 TIMER0_BRKIN1 output2 TIMER0_BRKIN2 TIMER0_CH0 output3 TIMER0_BRKIN3 TIMER0_CH1 TIMER0_CH2 output0 TIMER7_BRKIN0 output1 TIMER7_BRKIN1 TIMER0_CH3 TRIGSEL_TIMER7BR output2 TIMER7_BRKIN2 TIMER0_MCH0 output3 TIMER7_BRKIN3 TIMER0_MCH1 TIMER0_MCH2 output0 TIMER19_BRKIN0 TIMER0_MCH3 output1 TIMER19_BRKIN1 TRIGSEL_TIMER19B output2 TIMER19_BRKIN2...
Page 162 GD32E502xx User Manual Trigger Source Trigger select TRIGSEL Register TRIGSEL output Peripherals MFCOM_TRIG2 output2 TIMER20_ITI2 output3 TIMER20_ITI3 MFCOM_TRIG3 RTC_Alarm output0 TIMER1_ITI0 output1 TIMER1_ITI1 RTC_Second TRIGSEL_TIMER1IN output2 TIMER1_ITI2 TRIGSEL_IN12 output3 TIMER1_ITI3 TRIGSEL_IN13 Note: All output can select all input as trigger source except TIMERx_ITIx and TIMERx_BRKINx.
Page 163: Register Definition
GD32E502xx User Manual Register definition 7.5. TRIGSEL base address: 0x4001 8400 Trigger selection for EXTOUT0 register (TRIGSEL_EXTOUT0) 7.5.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). INSEL3[6:0] Reserved INSEL2[6:0] Reserved INSEL1[6:0] Reserved INSEL0[6:0] Bits Fields...
Page 164: Trigger Selection For Extout1 Register (Trigsel_Extout1)
GD32E502xx User Manual is used as the source of external output0 signal. For the detailed configuration, please refer to Table 7-1. Trigger input bit fields selection. Trigger selection for EXTOUT1 register (TRIGSEL_EXTOUT1) 7.5.2. Address offset: 0x04 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 165: Trigger Selection For Adc0 Register (Trigsel_Adc0)
GD32E502xx User Manual please refer to Table 7-1. Trigger input bit fields selection. Trigger selection for ADC0 register (TRIGSEL_ADC0) 7.5.3. Address offset: 0x08 Reset value: 0x0000 1E16 This register has to be accessed by word (32-bit). Reserved Reserved INSEL0[6:0] Bits Fields Descriptions TRIGSEL register lock.
Page 166: Trigger Selection For Dac Register (Trigsel_Dac)
GD32E502xx User Manual TRIGSEL register lock. This bit is set by softw are and cleared only by a system reset. When it is set, it disables w rite access to TRIGSEL_A DC1 register. 0: TRIGSEL_A DC1 register w rite is enabled. 1: TRIGSEL_A DC1 register w rite is disabled.
Page 167: Trigger Selection For Timer0_Brkin Register (Trigsel_Timer0Brkin)
GD32E502xx User Manual This register has to be accessed by word (32-bit). INSEL3[6:0] Reserved INSEL2[6:0] Reserved INSEL1[6:0] Reserved INSEL0[6:0] Bits Fields Descriptions TRIGSEL register lock. This bit is set by softw are and cleared only by a system reset. When it is set, it disables w rite access to TRIGSEL_ TIMER0IN register.
Page 168: Trigger Selection For Timer7_Iti Register (Trigsel_Timer7In)
GD32E502xx User Manual INSEL3[6:0] Reserved INSEL2[6:0] Reserved INSEL1[6:0] Reserved INSEL0[6:0] Bits Fields Descriptions TRIGSEL register lock. This bit is set by softw are and cleared only by a system reset. When it is set, it disables w rite access to TRIGSEL_TIMER0BRKIN register. 0: TRIGSEL_TIMER0BRKIN register w rite is enabled.
Page 169: Trigger Selection For Timer7_Brkin Register (Trigsel_Timer7Brkin)
GD32E502xx User Manual INSEL3[6:0] Reserved INSEL2[6:0] Reserved INSEL1[6:0] Reserved INSEL0[6:0] Bits Fields Descriptions TRIGSEL register lock. This bit is set by softw are and cleared only by a system reset. When it is set, it disables w rite access to TRIGSEL_TIMER7IN register. 0: TRIGSEL_TIMER7IN register w rite is enabled.
Page 170: Trigger Selection For Timer19_Iti Register (Trigsel_Timer19In)
GD32E502xx User Manual Reserved INSEL1[6:0] Reserved INSEL0[6:0] Bits Fields Descriptions TRIGSEL register lock. This bit is set by softw are and cleared only by a system reset. When it is set, it disables w rite access to TRIGSEL_TIMER7BRKIN register. 0: TRIGSEL_TIMER7BRKIN register w rite is enabled. 1: TRIGSEL_TIMER7BRKIN register w rite is disabled.
Page 171: Trigger Selection For Timer19_Brkin Register (Trigsel_Timer19Brkin)
GD32E502xx User Manual Reserved INSEL1[6:0] Reserved INSEL0[6:0] Bits Fields Descriptions TRIGSEL register lock. This bit is set by softw are and cleared only by a system reset. When it is set, it disables w rite access to TRIGSEL_TIMER19IN register. 0: TRIGSEL_TIMER19IN register w rite is enabled. 1: TRIGSEL_TIMER19IN register w rite is disabled.
Page 172: Trigger Selection For Timer20_Iti Register (Trigsel_Timer20In)
GD32E502xx User Manual Reserved INSEL1[6:0] Reserved INSEL0[6:0] Bits Fields Descriptions TRIGSEL register lock. This bit is set by softw are and cleared only by a system reset. When it is set, it disables w rite access to TRIGSEL_TIMER19BRKIN register. 0: TRIGSEL_TIMER19BRKIN register w rite is enabled. 1: TRIGSEL_TIMER19BRKIN register w rite is disabled.
Page 173: Trigger Selection For Timer20_Brkin Register (Trigsel_Timer20Brkin)
GD32E502xx User Manual Reserved INSEL1[6:0] Reserved INSEL0[6:0] Bits Fields Descriptions TRIGSEL register lock. This bit is set by softw are and cleared only by a system reset. When it is set, it disables w rite access to TRIGSEL_TIMER20IN register. 0: TRIGSEL_TIMER20IN register w rite is enabled. 1: TRIGSEL_TIMER20IN register w rite is disabled.
Page 174: Trigger Selection For Timer1_Iti Register (Trigsel_Timer1In)
GD32E502xx User Manual Reserved INSEL1[6:0] Reserved INSEL0[6:0] Bits Fields Descriptions TRIGSEL register lock. This bit is set by softw are and cleared only by a system reset. When it is set, it disables w rite access to TRIGSEL_TIMER20BRKIN register. 0: TRIGSEL_TIMER20BRKIN register w rite is enabled. 1: TRIGSEL_TIMER20BRKIN register w rite is disabled.
Page 175: Trigger Selection For Mfcom Register (Trigsel_Mfcom)
GD32E502xx User Manual Reserved INSEL1[6:0] Reserved INSEL0[6:0] Bits Fields Descriptions TRIGSEL register lock. This bit is set by softw are and cleared only by a system reset. When it is set, it disables w rite access to TRIGSEL_TIMER1IN register. 0: TRIGSEL_TIMER1IN register w rite is enabled. 1: TRIGSEL_TIMER1IN register w rite is disabled.
Page 176: Trigger Selection For Can0 Register (Trigsel_Can0)
GD32E502xx User Manual Reserved INSEL1[6:0] Reserved INSEL0[6:0] Bits Fields Descriptions TRIGSEL register lock. This bit is set by softw are and cleared only by a system reset. When it is set, it disables w rite access to TRIGSEL_MFCOM register. 0: TRIGSEL_MFCOM register w rite is enabled. 1: TRIGSEL_MFCOM register w rite is disabled.
Page 177: Trigger Selection For Can1 Register (Trigsel_Can1)
GD32E502xx User Manual Bits Fields Descriptions TRIGSEL register lock. This bit is set by softw are and cleared only by a system reset. When it is set, it disables w rite access to TRIGSEL_CA N0 register. 0: TRIGSEL_CA N0 register w rite is enabled. 1: TRIGSEL_CA N0 register w rite is disabled.
Page 178: General-Purpose And Alternate-Function I/Os (Gpio And Afio)
GD32E502xx User Manual General-purpose and alternate-function I/Os (GPIO and AFIO) 8.1. Overview There are up to 88 general purpose I/O pins (GPIO), named PA0~PA15, PB0~PB15, PC0~PC15, PD0~PD15， PE0~PE15， PF0~ PF7 for the device to implement logic input/output functions. Each GPIO port has related control and configuration registers to satisfy the requirements of specific applications.
Page 179: Figure 8-1. Basic Structure Of A General-Pupose I/O
GD32E502xx User Manual as floating (no pull-up and pull-down), pull-up or pull-down function by GPIO pull-up/pull-down registers (GPIOx_PUD). Table 8-1. GPIO configuration table PAD TYPE CTLy PUDy Floating GPIO pull-up INPUT pull-dow n Floating push-pull pull-up GPIO pull-dow n OUTPUT Floating open-drain pull-up...
Page 180: Gpio Pin Configuration
GD32E502xx User Manual GPIO pin configuration 8.3.1. During or just after the reset period, the alternative functions are all inactive and the GPIO ports are configured into the input floating mode that input disabled without Pull-Up(PU)/Pull- Down(PD) resistors. But the JTAG/Serial-Wired Debug pins are in input PU/PD mode after reset: PB7: JTDI in PU mode PB8: JTCK / SWCLK in PD mode...
Page 181: Input Configuration
GD32E502xx User Manual Input configuration 8.3.5. When GPIO pin is configured as input:  The schmitt trigger input is enabled.  The weak pull-up and pull-down resistors could be chosen.  Every AHB clock cycle the data present on the I/O pin is got to the port input status register.
Page 182: Analog Configuration
GD32E502xx User Manual Analog configuration 8.3.7. When GPIO pin is used as analog configuration:  The weak pull-up and pull-down resistors are disabled.  The output buffer is disabled.  The schmitt trigger input is disabled.  The port input status register of this I/O port bit is “0”. Figure 8-4.
Page 183: Gpio Locking Function
GD32E502xx User Manual Figure 8-5. Basic structure of Alternate function configuration Alternate Function Output Output driver protect I / O pin Alternate Function Input Input driver GPIO locking function 8.3.9. The locking mechanism allows the IO configuration to be protected. The protected registers are GPIOx_CTL, GPIOx_OMODE, GPIOx_OSPD, GPIOx_PUD and GPIOx_AFSELy (y=0, 1).
Page 184: Register Definition
GD32E502xx User Manual 8.4. Register definition GPIOA base address: 0x4800 0000 GPIOB base address: 0x4800 0400 GPIOC base address: 0x4800 0800 GPIOD base address: 0x4800 0C00 GPIOE base address: 0x4800 1000 GPIOF base address: 0x4800 1400 Port control register (GPIOx_CTL, x=A..F) 8.4.1.
Page 185 GD32E502xx User Manual 21:20 CTL10[1:0] Pin 10 configuration bits These bits are set and cleared by softw are. Refer to CTL0[1:0] description 19:18 CTL9[1:0] Pin 9 configuration bits These bits are set and cleared by softw are. Refer to CTL0[1:0] description 17:16 CTL8[1:0] Pin 8 configuration bits...
Page 186: Port Output Mode Register (Gpiox_Omode, X=A
GD32E502xx User Manual Port output mode register (GPIOx_OMODE, x=A..F) 8.4.2. Address offset: 0x04 Reset value: 0x0000 0000 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit) Reserved OM15 OM14 OM13 OM12 OM11 OM10 Bits Fields Descriptions 31:16 Reserved Must be kept at reset value OM15 Pin 15 output mode bit These bits are set and cleared by softw are.
Page 187: Port Output Speed Register (Gpiox_Ospd, X=A
GD32E502xx User Manual These bits are set and cleared by softw are. Refer to OM0 description Pin 6 output mode bit These bits are set and cleared by softw are. Refer to OM0 description Pin 5 output mode bit These bits are set and cleared by softw are. Refer to OM0 description Pin 4 output mode bit These bits are set and cleared by softw are.
Page 188 GD32E502xx User Manual These bits are set and cleared by softw are. Refer to OSPD0[1:0] description 29:28 OSPD14[1:0] Pin 14 output max speed bits These bits are set and cleared by softw are. Refer to OSPD0[1:0] description 27:26 OSPD13[1:0] Pin 13 output max speed bits These bits are set and cleared by softw are.
Page 189: Port Pull-Up/Down Register (Gpiox_Pud, X=A
GD32E502xx User Manual Refer to OSPD0[1:0] description OSPD2[1:0] Pin 2 output max speed bits These bits are set and cleared by softw are. Refer to OSPD0[1:0] description OSPD1[1:0] Pin 1 output max speed bits These bits are set and cleared by softw are. Refer to OSPD0[1:0] description OSPD0[1:0] Pin 0 output max speed bits...
Page 190 GD32E502xx User Manual These bits are set and cleared by softw are. Refer to PUD0[1:0] description 21:20 PUD10[1:0] Pin 10 pull-up or pull-dow n bits These bits are set and cleared by softw are. Refer to PUD0[1:0] description 19:18 PUD9[1:0] Pin 9 pull-up or pull-dow n bits These bits are set and cleared by softw are.
Page 191: Port Input Status Register (Gpiox_Istat, X=A
GD32E502xx User Manual Port input status register (GPIOx_ISTAT, x=A..F) 8.4.5. Address offset: 0x10 Reset value: 0x0000 XXXX This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit) Reserved ISTAT15 ISTAT14 ISTAT13 ISTAT12 ISTAT11 ISTAT10 ISTAT9 ISTAT8 ISTAT7 ISTAT6 ISTAT5 ISTAT4 ISTAT3 ISTAT2 ISTAT1...
Page 192: Port Configuration Lock Register (Gpiox_Lock, X=A
GD32E502xx User Manual Reset value: 0x0000 0000 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit) CR15 CR14 CR13 CR12 CR11 CR10 BOP15 BOP14 BOP13 BOP12 BOP11 BOP10 BOP9 BOP8 BOP7 BOP6 BOP5 BOP4 BOP3 BOP2 BOP1 BOP0 Bits Fields Descriptions 31:16...
Page 193: Alternate Function Selected Register 0 (Gpiox_Afsel0, X=A
GD32E502xx User Manual sequence. 15:0 Port lock bit y(y=0..15) These bits are set and cleared by softw are. 0: Port configuration not locked 1: Port configuration locked Alternate function selected register 0 (GPIOx_AFSEL0, x=A..F) 8.4.9. Address offset: 0x20 Reset value: 0x0000 0000 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit) SEL7[3:0] SEL6[3:0]...
Page 194: Alternate Function Selected Register 1 (Gpiox_Afsel1, X=A
GD32E502xx User Manual Refer to SEL0[3:0] description SEL0[3:0] Pin 0 alternate function selected These bits are set and cleared by softw are. 0000: AF0 selected (reset value) 0001: AF1 selected 0010: AF2 selected 0011: AF3 selected 0100: AF4 selected 0101: AF5 selected 0110: AF6 selected 0111: AF7 selected 1000: AF8 selected...
Page 195: Bit Clear Register (Gpiox_Bc, X=A
GD32E502xx User Manual Refer to SEL8[3:0] description 15:12 SEL11[3:0] Pin 11 alternate function selected These bits are set and cleared by softw are. Refer to SEL8[3:0] description 11:8 SEL10[3:0] Pin 10 alternate function selected These bits are set and cleared by softw are. Refer to SEL8[3:0] description SEL9[3:0] Pin 9 alternate function selected...
Page 196: Port Bit Toggle Register (Gpiox_Tg, X=A
GD32E502xx User Manual These bits are set and cleared by softw are. 0: No action on the corresponding OCTLy bit 1: Clear the corresponding OCTLy bit Port bit toggle register (GPIOx_TG, x=A..F) 8.4.12. Address offset: 0x2C Reset value: 0x0000 0000 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit) Reserved TG15...
Page 197: Multi-Function Communication Interface (Mfcom)
GD32E502xx User Manual Multi-function communication Interface (MFCOM) 9.1. Overview The MFCOM is a highly configurable module provide emulation of a variety of serial communication protocols and flexible timers. 9.2. Characteristics  Continuous data transfer configuration  Shift register with dual cache regions supports continuous data transfer. ...
Page 198: Function Overview
GD32E502xx User Manual Access the MFCOM register through the AHB bus clock, MFCOM has 4 timers, 4 shifters and 8 pins. Can select the shifter's pin input and output through SPSEL[2:0] bit. By configuring INSRC, can select the input source of the shifte (the output of the shifter or the input of the pin are optional).
Page 199: Figure 9-2. Shifter Microarchitecture
GD32E502xx User Manual Figure 9-2. Shifter microarchitecture INSRC TMPL Timer start/stop Pin out Shifter x output Shifter x SSTOP SSTART Table 9-1. Mode of shifter SSTAT、Interrupt SERR、Interrupt Shifter w orking Mode DMA request setting m echanism setting conditions conditions the shifter w ill load data has been loaded data from the shifter from the shifter buffer...
Page 200: Timer
GD32E502xx User Manual SSTAT、Interrupt SERR、Interrupt Shifter w orking Mode DMA request setting m echanism setting conditions conditions assigned timer. The shifter w ill shift data in and continuously check A match occurs, Match for a match result returns the current A match occurs.
Page 201 GD32E502xx User Manual configured by a 16-bit counter. When the 16-bit counter equal to zero and decrement, the timer output switches and the counter is reloaded from the comparison register. When the 16- bit counter equal to zero and decrement, the timer comparison event occurs and the timer status flag is set.
Page 202: Pin
GD32E502xx User Manual decrement only occurs when the low 8-bits equal to zero and decrement. A timer comparison event is triggered when the timer counter decrements to 0. The trigger of the timer comparison event will cause the timer counter to load the contents of the comparison register, the timer output to the toggle, the send shift register of any configuration to load, and the receive shift register of any configuration to store.
Page 203: Interrupts And Dma Requests
GD32E502xx User Manual on a bidirectional output. Any timer or shifter may be driven by another timer or shifter, configured to control output so that data can be output bidirectional on one pin. Pin synchronization When a pin is configured as input, the input signal is first synchronized with the MFCOM clock before the signal is used by a timer or shifter.
Page 204: Typical Configuration Of Application
GD32E502xx User Manual or more MFCOM timers can be triggered. Output triggers The output trigger of each MFCOM timer is equal to the timer output, and the timer output is not affected by the timer's pin polarity configuration. Typical configuration of application 9.4.7.
Page 205 GD32E502xx User Manual can be written to an SBUF[7:0] to initiate an 8-bit transmission, using the shifter status flag bit to determine when to use an interrupt or DMA request to write. Supports the MSB first transfer write to the SBUFBBS[7:0] register instead. UART receive UART receivers use one timer, one shifter, and one pin support, while supporting RTS requires two timers and two pins.
Page 206 GD32E502xx User Manual 0. Can invert input data by setting PINPL. Set the value of register MFCOM_TMCMPx as 0x00000F01, configure 8-bit transfer with baud rate of divide by 4 of the MFCOM clock. Set TMCVALUE [15:8] = (number of bits x 2) - 1.
Page 207 GD32E502xx User Manual with input data on pin1. Set the value of register MFCOM_TMCMPx as 0x00003F01, configure 32-bit transfer with baud rate of divide by 4 of the MFCOM clock. Set TMCVALUE [15:8] = (number of bits x 2) - 1. Set TMCVALUE [7:0] = (baud rate divider / 2) - 1. Set the bits TMOUT[1:0], TMDIS[2:0], TMEN[2:0] TMSTOP[1:0], and TMSTART as 0b01, 0b010, 0b010, 0b10, and 0b1 in register MFCOM_TMCFGx respectively, configure start bit, stop bit, enable on trigger high and disable on compare, initial clock state is logic 0.
Page 208 GD32E502xx User Manual Set the bits TRIGSEL[3:0], TRIGPL, TRIGSRC, TMPCFG[1:0], TMPSEL[2:0], and TMMOD[1:0] as 0b0001, 0b1, 0b1, 0b11, 0b010, and 0b01 in register MFCOM_TMCTLx respectively, configure dual 8-bit counter using pin 2 output (shift clock), with shifter 0 flag as the inverted trigger. Set PINPL to invert the output shift clock. Set TMDIS[2:0] = 0b011 to keep slave select asserted for as long as there is data in the transmit buffer.
Page 209 GD32E502xx User Manual clock state is logic 0 and decrement on pin input. Set the bits TRIGSEL[3:0], TRIGPL, TRIGSRC, TMPSEL[2:0], and TMMOD[1:0] as 0b0110, 0b1, 0b1, 0b010, and 0b11 in register MFCOM_TMCTLx respectively, configure 16-bit counter using pin 2 input (shift clock), with pin 3 input (slave select) as the inverted trigger.
Page 210 GD32E502xx User Manual each word. When receiving, the transmitter must send 0xFF for tristate output. MFCOM waits for a write to the transfer data buffer before enabling SCL generation. Data transfer is supported using DMA. The shift error flag will be set when under-send or over-receive occurs. MFCOM inserts a stop bit after each word to generate/verify ACK/NACK.
Page 211 GD32E502xx User Manual respectively, configure start bit, stop bit, enable on trigger high, disable on compare, reset if output equals pin. Initial clock state is logic 0 and is not affected by reset. Set the bits TRIGSEL[3:0], TRIGPL, TRIGSRC, TMPCFG[1:0], TMPSEL[2:0], and TMMOD[1:0] as 0b0001, 0b1, 0b1, 0b01, 0b001, and 0b01 in register MFCOM_TMCTLx respectively, configure dual 8-bit counter using pin 1 output enable (SCL open drain), with shifter 0 flag as the inverted trigger.
Page 212 GD32E502xx User Manual with input data on pin 1. Set the value of register MFCOM_TMCMPx as 0x00003F01, configure 32-bit transfer with baud rate of divide by 4 of the MFCOM clock. Set TMCVALUE [15:8] = (number of bits x 2) - 1. Set TMCVALUE [7:0] = (baud rate divider / 2) - 1. Set the bits TMEN[2:0] and TMSTART as 0b010, and 0b1 in register MFCOM_TMCFGx respectively, configure start bit, enable on trigger high and never disable.
Page 213 GD32E502xx User Manual Set the bits TMSEL[1:0], SPCFG[1:0] and SMOD[2:0] as 0b01, 0b11 and 0b010 in register MFCOM_SCTLx respectively, configure transmit using timer 1 on rising edge of shift clock with output data on pin 0. Set the bits in register MFCOM_SCFG(x+1) as default value, start and stop bit disabled. Set the bits TMSEL[1:0], TMPL, SPSEL[2:0] and SMOD[2:0] as 0b01, 0b1, 0b001, and 0b001 in register MFCOM_SCTL(x+1) respectively, configure receive using timer 1 on falling edge of shift clock with input data on pin 1.
Page 214: Register Definition
GD32E502xx User Manual 9.5. Register definition MFCOM base address: 0x4003 8400 Control register (MFCOM_CTL) 9.5.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved SWRSTE MFCOME Reserved Bits Fields Descriptions 31:2 Reserved Must be kept at reset value SWRSTEN Softw are reset enable...
Page 215: Shifter Status Register (Mfcom_Sstat)
GD32E502xx User Manual 31:8 Reserved Must be kept at reset value PDATA[7:0] data of pins The input/output data of each MFCOM pins. Shifter status register (MFCOM_SSTAT) 9.5.3. Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved SSTAT[3:0]...
Page 216: Timer Status Register (Mfcom_Tmstat)
GD32E502xx User Manual Reserved SERR[3:0] Bits Fields Descriptions 31:4 Reserved Must be kept at reset value SERR[3:0] Shifter x error flags The shift error flag is set w hen one of the follow ing events occurs: SMOD = Receive, MFCOM_SBUF overrun, or the receive start or stop bit does not match the expected value.
Page 217: Shifter Status Interrupt Enable Register (Mfcom_Ssien)
GD32E502xx User Manual In 16-bit counter mode, the timer status flag w ill be set w hen the 16-bit counter decrements to zero and the decrement is active. This bit can be cleared by softw are w riting 1. 0: Timer x status flag is not set. 1: Timer x status flag is set.
Page 218: Timer Status Interrupt Enable Register (Mfcom_Tmsien)
GD32E502xx User Manual 0: Shifter error flags do not generate an interrupt 1: Shifter error flags generate an interrupt Timer status interrupt enable register (MFCOM_TMSIEN) 9.5.8. Address offset: 0x20 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved TMSIEN[3:0]...
Page 219: Shifter Control X Register (Mfcom_Sctlx)
GD32E502xx User Manual Shifter control x register (MFCOM_SCTLx) 9.5.10. Address offset: 0x80 + 0x04 * x, (x = 0 to 3) Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved TMSEL[1:0] TMPL Reserved SPCFG[1:0] Reserved SPSEL[2:0] SPPL Reserved...
Page 220: Shifter Configuration X Register (Mfcom_Scfgx)
GD32E502xx User Manual 000: Disabled. 001: Receive mode. 010: Transmit mode. 011: Reserved. 100: Match store mode. 101: Match continuous mode. 110: Reserved. 111: Reserved. Shifter configuration x register (MFCOM_SCFGx) 9.5.11. Address offset: 0x100 + 0x004 * x, (x = 0 to 3) Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 221: Shifter Buffer X Register (Mfcom_Sbufx)
GD32E502xx User Manual SSTART[1:0] Shifter start bit 00: Disable the start bit, send data w hen the start bit is enabled 01: Disable start bit, send data on first shift 10: The start bit is valid at low level before the first shift to send data in transmit mode.
Page 222: Shifter Buffer X Byte Swapped Register (Mfcom_Sbufbysx)
GD32E502xx User Manual This register has to be accessed by word (32-bit). SBUFBIS[31:16] SBUFBIS[15:0] Bits Fields Descriptions 31:0 SBUFBIS[31:0] Shift buffer bit sw apped Same as the MFCOM_SBUF register, except that the read/w rite register is bit sw apped, and reads return SBUF[0:31]. Shifter buffer x byte swapped register (MFCOM_SBUFBYSx) 9.5.14.
Page 223: Timer Control X Register (Mfcom_Tmctlx)
GD32E502xx User Manual Bits Fields Descriptions 31:0 SBUFBBS[31:0] Shift buffer bit byte sw apped Same as the MFCOM_SBUF register, except that the read/w rite register is bit sw apped w ithin each byte, and reads return {SBUF[24:31], SBUF[16:23], SBUF[8:15], SBUF[0:7]}. Timer control x register (MFCOM_TMCTLx) 9.5.16.
Page 224: Timer Configuration X Register (Mfcom_Tmcfgx)
GD32E502xx User Manual 1110: Pin7 1111: Timer 2 trigger TRIGPL Trigger polarity 0: Trigger is activated at high 1: Trigger is activated at low TRIGSRC Trigger source 0: Select external trigger 1: Select internal trigger 21:18 Reserved Must be kept at reset value 17:16 TMPCFG[1:0] Timer pin configuration...
Page 225 GD32E502xx User Manual Reserved TMDIS[2:0] Reserved TMEN[2:0] Reserved TMSTOP[1:0] Reserved TMSTART Reserved Bits Fields Descriptions 31:26 Reserved Must be kept at reset value 25:24 TMOUT[1:0] Timer output Configures the initial state of the timer output and w hether it is affected by the timer reset.
Page 226: Timer Compare X Register (Mfcom_Tmcmpx)
GD32E502xx User Manual 101: Disabled on pin rising or falling edge and provided trigger is high 110: Disabled on trigger falling edge 111: Reserved Reserved Must be kept at reset value 10:8 TMEN[2:0] Timer enable Configure the conditions that enable the timer and start decrement 000: Alw ays enabled 001: Enabled on timer x-1 enable 010: Enabled on trigger high...
Page 227 GD32E502xx User Manual 31:16 Reserved Must be kept at reset value 15:0 TMCVALUE[15:0] Timer compare value The timer compare value is loaded into the timer counter w hen the timer is first enabled, the timer is reset, and the timer is reduced to zero. 8-bit baud counter mode：...
Page 228: Crc Calculation Unit (Crc)
GD32E502xx User Manual CRC calculation unit (CRC) Overview 10.1. A cyclic redundancy check (CRC) is an error-detecting code commonly used in digital networks and storage devices to detect accidental changes to raw data. This CRC calculation unit can be used to calculate 7/8/16/32 bit CRC code within user configurable polynomial.
Page 229: Function Overview
GD32E502xx User Manual Function overview 10.3.  CRC calculation unit is used to calculate the 32-bit raw data, and CRC_DATA register will receive the raw data and store the calculation result. If the CRC_DATA register has not been cleared by setting the CRC_CTL register, the new input raw data will be calculated based on the result of previous value of CRC_DATA.
Page 230: Register Definition
GD32E502xx User Manual Register definition 10.4. CRC base address: 0x4002 3000 Data register (CRC_DATA) 10.4.1. Address offset: 0x00 Reset value: 0xFFFF FFFF This register has to be accessed by word (32-bit). DATA[31:16] DATA[15:0] Bits Fields Descriptions 31:0 DATA[31:0] CRC calculation result bits Softw are w rites and reads.
Page 231: Control Register (Crc_Ctl)
GD32E502xx User Manual by any other peripheral. The CRC_CTL register w ill generate no effect to the byte. Control register (CRC_CTL) 10.4.3. Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved REV_O REV_I[1:0] PS[1:0]...
Page 232: Polynomial Register (Crc_Poly)
GD32E502xx User Manual This register has to be accessed by word (32-bit). IDATA[31:16] IDATA[15:0] Bits Fields Descriptions 31:0 IDATA[31:0] Configurable initial CRC data value When RST bit in CRC_CTL asserted, CRC_DATA w ill be programmed to this value. Polynomial register (CRC_POLY) 10.4.5.
Page 233: Direct Memory Access Controller (Dma)
GD32E502xx User Manual Direct memory access controller (DMA) 11.1. Overview The direct memory access (DMA) controller provides a hardware method of transferring data between peripherals and/or memory without intervention from the CPU, thereby freeing up bandwidth for other system functions. Data can be quickly moved by DMA between peripherals and memory as well as memory and memory without any CPU actions.
Page 234: Block Diagram
GD32E502xx User Manual 11.3. Block diagram Figure 11-1. Block diagram of DMA AHB slave interface Configuration … dma_req Channel 6 AHB master dma_ack interface Channel 2 dma_req Master dma_ack Port Channel 1 dma_req dma_ack Channel 0 dma_req dma_ack Memory control state &...
Page 235: Table 11-1. Dma Transfer Operation
GD32E502xx User Manual Table 11-1. DMA transfer operation Transfer size Transfer operations Source Destination Source Destination 1: Read B3B2B1B0[31:0] @0x0 1: Write B3B2B1B0[31:0] @0x0 2: Read B7B6B5B4[31:0] @0x4 2: Write B7B6B5B4[31:0] @0x4 32 bits 32 bits 3: Read BBBAB9B8[31:0] @0x8 3: Write BBBAB9B8[31:0] @0x8 4: Read BFBEBDBC[31:0] @0xC 4: Write BFBEBDBC[31:0] @0xC...
Page 236: Peripheral Handshake
GD32E502xx User Manual The CNT bits in the DMA_CHxCNT register control how many data to be transmitted on the channel and must be configured before enable the CHEN bit in the register. During the transmission, the CNT bits indicate the remaining number of data items to be transferred. The DMA transmission is disabled by clearing the CHEN bit in the DMA_CHxCTL register.
Page 237: Arbitration
GD32E502xx User Manual Arbitration 11.4.3. When two or more requests are received at the same time, the arbiter determines which request is served based on the priorities of channels. There are two-stage priorities, including the software priority and the hardware priority. The arbiter determines which channel is selected to respond according to the following priority rules: ...
Page 238: Interrupt
GD32E502xx User Manual 1. Read the CHEN bit and judge whether the channel is enabled or not. If the channel is enabled, clear the CHEN bit by software. When the CHEN bit is read as ‘0’, configuring and starting a new DMA transfer is allowed. 2.
Page 239: Dma Request Mapping
GD32E502xx User Manual Figure 11-3. DMA interrupt logic Note: “x” indicates channel number (x=0…6). DMA request mapping 11.4.9. The DMA requests of a channel are coming from the AHB/APB peripherals through the corresponding channel output of DMAMUX request multiplexer, refer to Table 12-3.
Page 240: Register Definition
GD32E502xx User Manual 11.5. Register definition DMA base address: 0x4002 0000 DMA1 base address: 0x4002 0400 Note: For DMA1 having 5 channels, all bits related to channel 5 and channel 6 in the following registers are not suitable for DMA1 Interrupt flag register (DMA_INTF) 11.5.1.
Page 241: Interrupt Flag Clear Register (Dma_Intc)
GD32E502xx User Manual Interrupt flag clear register (DMA_INTC) 11.5.2. Address offset: 0x04 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved ERRIFC6 HTFIFC6 FTFIFC6 GIFC6 ERRIFC5 HTFIFC5 FTFIFC5 GIFC5 ERRIFC4 HTFIFC4 FTFIFC4 GIFC4 ERRIFC3 HTFIFC3 FTFIFC3 GIFC3 ERRIFC2 HTFIC2 FTFIFC2 GIFC2...
Page 242 GD32E502xx User Manual Bits Fields Descriptions 31:15 Reserved Must be kept at reset value. Memory to Memory mode Softw are set and cleared 0: Disable Memory to Memory mode 1: Enable Memory to Memory mode This bit can not be w ritten w hen CHEN is ‘1’. 13:12 PRIO[1:0] Priority level...
Page 243: Channel X Counter Register (Dma_Chxcnt)
GD32E502xx User Manual 0: Disable circular mode 1: Enable circular mode This bit can not be w ritten w hen CHEN is ‘1’. Transfer direction Softw are set and cleared 0: Read from peripheral and w rite to memory 1: Read from memory and w rite to peripheral This bit can not be w ritten w hen CHEN is ‘1’.
Page 244: Channel X Peripheral Base Address Register (Dma_Chxpaddr)
GD32E502xx User Manual 15:0 CNT[15:0] Transfer counter These bits can not be w ritten w hen CHEN in the DMA_CHxCTL register is ‘1’. This register indicates how many transfers remain. Once the channel is enabled, it is read-only, and decreases after each DMA transfer. If the register is zero, no transaction can be issued w hether the channel is enabled or not.
Page 245 GD32E502xx User Manual Bits Fields Descriptions 31:0 MADDR[31:0] Memory base address These bits can not be w ritten w hen CHEN in the DMA_CHxCTL register is ‘1’. When MWIDTH in the DMA_CHxCTL register is 01 (16-bit), the LSB of these bits is ignored.
Page 246: Dma Request Multiplexer (Dmamux)
GD32E502xx User Manual DMA request multiplexer (DMAMUX) 12.1. Overview DMAMUX is a transmission scheduler for DMA requests. The DMAMUX request multiplexer is used for routing a DMA request line between the peripherals / generated DMA request (from the DMAMUX request generator) and the DMA controller. Each DMAMUX request multiplexer channel selects a unique DMA request line, unconditionally or synchronously with events from its DMAMUX synchronization inputs.
Page 247: Block Diagram
GD32E502xx User Manual 12.3. Block diagram Figure 12-1. Block diagram of DMAMUX Request multiplexer Slave Port Channel 11 Channel 2 Channel 1 Peri_reqx To DMA controller: Channel 0 Reqx_out Sync Counter underrun: Reqx_in Evtx_out Configuration Register Input selector Synchronization inputs: Syncx_in Gen_reqx Request generator...
Page 248: Dmamux Signals
GD32E502xx User Manual DMAMUX request generator.  Trigger inputs (Trgx_in) source from internal or external signals. DMAMUX signals 12.4.1. Table 12-1. DMAMUX signals Signal nam e Discription DMAMUX request multiplexer inputs (from peripheral requests and request Reqx_in generator channels) Peri_reqx DMAMUX DMA request line inputs from peripherals Gen_reqx DMAMUX generated DMA request from request generator...
Page 249: Figure 12-2. Synchronization Mode
GD32E502xx User Manual If the channel event generation is enabled by setting EVGEN bit, the number of DMA requests before an output event generation is NBR[4:0] + 1. Note: The NBR[4:0] bits value shall only be written by software when both synchronization enable bit SYNCEN and event generation enable EVGEN bit of the corresponding request multiplexer channel x are disabled.
Page 250: Figure 12-3. Event Generation
GD32E502xx User Manual Note: If a synchronization input event occurs when there is no pending selected input DMA request line, the input event is discarded. The following asserted input request lines will not be routed to the DMAMUX multiplexer channel output until a synchronization input event occurs again.
Page 251: Dmamux Request Generator
GD32E502xx User Manual there will be a synchronization overrun due to the absence of a DMA acknowledge (that is, no served request) received from the DMA controller. DMAMUX request generator 12.4.3. The DMAMUX request generator produces DMA requests upon trigger input event. Its component unit is the request generator channels.
Page 252: Channel Configurations
GD32E502xx User Manual Channel configurations 12.4.4. The following sequence should be followed to configure a DMAMUX channel y and the related DMA channel x: Set and configure the DMA channel x completely, except enabling the channel x. Set and configure the related DMAMUX channel y completely. Configure the CHEN bit with ‘1’...
Page 253: Table 12-3. Request Multiplexer Input Mapping
GD32E502xx User Manual A DMA request is sourced either from the peripherals or from the DMAMUX request generator, the sources can refer to Table 12-3. Request multiplexer input mapping, configured by the MUXID[6:0] bits in the DMAMUX_RM_CHxCFG register for the DMAMUX request multiplexer channel x.
Page 254 GD32E502xx User Manual Request m ultiplexer channel input identification Source MUXID[6:0] TIMER1_CH3 TIMER1_TI TIMER1_UP TIMER7_CH0 TIMER7_CH1 TIMER7_CH2 TIMER7_CH3 TIMER7_TI TIMER7_UP TIMER7_CO TIMER7_MCH0 TIMER7_MCH1 TIMER7_MCH2 TIMER7_MCH3 CAN1 CAN0 USART0_RX USART0_TX USART1_RX USART1_TX USART2_RX USART2_TX TIMER5_UP TIMER6_UP TIMER19_CH0 TIMER19_CH1 TIMER19_CH2 TIMER19_CH3 TIMER19_TI TIMER19_UP TIMER19_CO TIMER19_MCH0...
Page 255: Table 12-4. Trigger Input Mapping
GD32E502xx User Manual Request m ultiplexer channel input identification Source MUXID[6:0] TIMER20_TI TIMER20_UP TIMER20_CO TIMER20_MCH0 TIMER20_MCH1 TIMER20_MCH2 TIMER20_MCH3 Trigger input mapping The DMA request trigger input for the DMAMUX request generator channel x is selected through the TID[4:0] bits in DMAMUX_RG_CHxCFG register, the sources can refer to Table 12-4.
Page 256: Table 12-5. Synchronization Input Mapping
GD32E502xx User Manual Trigger input identification Source TID[4:0] Reserved Reserved Reserved Reserved Synchronization input mapping The synchronization input is selected by SYNCID[4:0] bits in the DMAMUX_RM_CHxCFG register, the sources can refer to Table 12-5. Synchronization input mapping. Table 12-5. Synchronization input mapping Synchronization input Source identification SYNCID[4:0]...
Page 257: Register Definition
GD32E502xx User Manual 12.5. Register definition DMAMUX base address: 0x4002 0800 Request multiplexer channel configuration register 12.5.1. (DMAMUX_RM_CHxCFG) x = 0...11, where x is a channel number Address offset: 0x00 + 0x04 × x Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved SYNCID[4:0] NBR[4:0]...
Page 258: Request Multiplexer Channel Interrupt Flag Register (Dmamux_Rm_Intf)
GD32E502xx User Manual 1: Enable event generation SOIE Synchronization overrun interrupt enable 0: Disable interrupt 1: Enable interrupt Reserved Must be kept at reset value. MUXID[6:0] Multiplexer input identification Selects the input DMA request in multiplexer input sources. Request multiplexer channel interrupt flag register (DMAMUX_RM_INTF) 12.5.2.
Page 259: Request Generator Channel X Configuration Register (Dmamux_Rg_Chxcfg)
GD32E502xx User Manual Bits Fields Descriptions 31:12 Reserved Must be kept at reset value. 11:0 SOIFCx Clear bit for synchronization overrun event flag of request multiplexer channel x (x=0..11) Writing 1 clears the corresponding overrun flag SOIFx in the DMAMUX_RM_ INT F register.
Page 260: Request Generator Interrupt Flag Register (Dmamux_Rg_Intf)
GD32E502xx User Manual 0: Disable interrupt 1: Enable interrupt Reserved Must be kept at reset value. TID[4:0] Trigger input identification Selects the DMA request trigger input source. Request generator interrupt flag register (DMAMUX_RG_INTF) 12.5.5. Address offset: 0x140 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 261 GD32E502xx User Manual 31:4 Reserved Must be kept at reset value. TOIFCx Clear bit for trigger overrun event flag of request generator channel x (x=0..3) Writing 1 in each bit clears the corresponding overrun flag TOIFx in the DMAMUX_RG_INTF register.
Page 262: Debug (Dbg)
GD32E502xx User Manual Debug (DBG) Introduction 13.1. The GD32E502xx series provide a large variety of debug and test features. They are implemented with a standard configuration of the Arm CoreSightTM module together with a ® daisy chained standard TAP controller. Debug function is integrated into the Arm ®...
Page 263: Jtag Daisy Chained Structure
GD32E502xx User Manual Table 13-1. Pin assignment Debug interface JTDI JTCK/SWCLK JTMS/SWDIO NJTRST JTDO By default, 5-pin standard JTAG debug mode is chosen after reset. Users can also use JT AG function without NJTRST pin, then the PB3 can be used to other GPIO functions (NJTRST tied to 1 by hardware).
Page 264: Debug Support For Timer, I2C, Wwdgt And Fwdgt
GD32E502xx User Manual When DSLP_HOLD bit in DBG control register (DBG_CTL) is set and entering the deep-sleep mode, the clock of AHB bus and system clock are provided by CK_IRC8M, and the debugger can debug in deep-sleep mode. When SLP_HOLD bit in DBG control register (DBG_CTL) is set and entering the sleep mode, the clock of AHB bus for CPU is not closed, and the debugger can debug in sleep mode.
Page 265: Registers Definition
GD32E502xx User Manual Registers definition 13.4. DEBUG base address: 0xE004 4000 ID code register (DBG_ID) 13.4.1. Address offset: 0x00 Read only This register has to be accessed by word (32-bit). ID_CODE[31:16] ID_CODE[15:0] Bits Fields Descriptions 31:0 ID_CODE[31:0] DBG ID code register These bits read by softw are.
Page 266 GD32E502xx User Manual 1: Hold the TIMER10 counter for debug w hen core halted. 29:24 Reserved Must be kept at reset value. CAN1_HOLD CAN1 hold bit This bit is set and reset by softw are. 0: no effect 1: Hold the CAN1 counter for debug w hen core halted. CAN0_HOLD CAN0 hold bit This bit is set and reset by softw are.
Page 267 GD32E502xx User Manual 0: no effect 1: Hold the TIMER1 counter for debug w hen core halted. TIMER0_HOLD TIMER0 hold bit This bit is set and reset by softw are. 0: no effect 1: Hold the TIMER0 counter for debug w hen core halted. WWDGT_HOLD WWDGT hold bit This bit is set and reset by softw are.
Page 268: Analog-To-Digital Converter (Adc)
GD32E502xx User Manual Analog-to-digital converter (ADC) Overview 14.1. A 12-bit successive approximation analog-to-digital converter module(ADC) is integrated on the MCU chip, which can sample analog signals from 16 external channels and 2 internal channels. The 18 ADC sampling channels all support a variety of operation modes. After sampling and conversion, the conversion results can be stored in the corresponding data registers according to the least significant bit (LSB) alignment or the most significant bit (MSB) alignment.
Page 269: Pins And Internal Signals
GD32E502xx User Manual – Oversampling ratio adjustable from 2x to 256x. – Programmable data shift up to 8-bit.  Module supply requirements: 2.7V to 5.5V, and typical power supply voltage is 5V.  ≤V ≤V Channel input range: V REFN REFP.
Page 270: Function Overview
GD32E502xx User Manual Function overview 14.4. Figure 14-1. ADC module block diagram watch dog event 0/1 Analog watchdog watch dog Trig select event 0/1 ETSRC Interrupt Routine channels Channel Management ADC_IN0 ADC_IN1 GPIO Over ADC_IN15 Routine data registers SAR ADC （16 bits）...
Page 271: Adc Clock
GD32E502xx User Manual Wait until CLB=0. ADC clock 14.4.2. The CK_ADC clock is synchronous with the AHB clock and provided by the clock controller. ADC clock can be divided and configured by RCU controller. 14.4.3. ADC enable The ADCON bit on the ADC_CTL1 register is the enable switch of the ADC module. The ADC module will keep in reset state if this bit is 0.
Page 272: Figure 14-3. Continuous Operation Mode
GD32E502xx User Manual Make sure the DISRC, SM in the ADC_CTL0 register and CTN bit in the ADC_CTL1 register are reset. Configure RSQ0 in ADC_RSQ2 register with the analog channel number. Configure ADC_SAMPTx register. Configure ETERC and ETSRC bits in the ADC_CTL1 register if in need. Set the SWRCST bit, or generate a TRIGSEL trigger for the routine sequence.
Page 273: Figure 14-4. Scan Operation Mode, Continuous Disable
GD32E502xx User Manual Scan operation mode The scan operation mode will be enabled when SM bit in the ADC_CTL0 register is set. In this mode, the ADC performs conversion on the channels with a specific sequence specified in the ADC_RSQ0~ADC_RSQ2 registers. When the ADCON has been set high, the ADC samples and converts specified channels one by one in the routine sequence till the end of the routine sequence, once the corresponding software trigger or TRIGSEL trigger is active.
Page 274: Conversion Result Threshold Monitor Function
GD32E502xx User Manual the ADC_CTL0 register. When the corresponding software trigger or TRIGSEL trigger is active, ADC samples and converts next channels configured ADC_RSQ0~ADC_RSQ2 registers until all the channels of routine sequence are done. The EOC will be set after every circle of the routine sequence. An interrupt will be generated if the EOCIE bit is set.
Page 275: Data Alignment
GD32E502xx User Manual watchdog 1 can be configured in the ADC_WDT1 register. 14.4.7. Data storage mode The alignment of data stored after conversion can be specified by DAL bit in the ADC_CTL1 register. Figure 14-7. Data storage mode of 12-bit resolution Figure 14-8.
Page 276: External Trigger Configuration
GD32E502xx User Manual by the SPTn[2:0] bits in the ADC_SAMPT0 and ADC_SAMPT1 registers. A different sample time can be specified for each channel. For 12-bits resolution, the total sampling and conversion time is “sampling time + 12.5” CK_ADC cycles. For example: CK_ADC = 15MHz and sample time is 2.5 cycles, the total time is “2.5+12.5”...
Page 277: Programmable Resolution (Dres)
GD32E502xx User Manual Enable the temperature sensor by setting the TSVEN bit in the ADC control register 1 (ADC_CTL1). Start the ADC conversion by setting the ADCON bit or by the triggers. Read the internal temperature sensor output voltage (V ), and get the temperature temperature using the following formula (14-1):...
Page 278: On-Chip Hardware Oversampling
GD32E502xx User Manual 433 ns 600 ns On-chip hardware oversampling 14.4.13. The on-chip hardware oversampling circuit performs data preprocessing to offload the CPU. It can handle multiple conversions and average them into a single data with inc reased data width, up to 16-bit. It provides a result with the following form, where N and M can be adjusted, and D (n) is the n-th output digital signal of the ADC: Result=...
Page 279: Adc Sync Mode
GD32E502xx User Manual Figure 14-12. Numerical example with 5-bits shift and rounding Table 14-5. Maximum output results for N and M (Grayed values indicates truncation) below gives the data format for the various N and M combination, for a raw conversion data equal to 0xFFF.
Page 280: Free Mode
GD32E502xx User Manual routine data register (ADC0_RDATA). The modes in Table 14-6. ADC sync mode table can be configured. In ADC sync mode, the DMA bit must be set even if it is not used. The converted data of ADC1 routine channel can be read from the ADC0 routine data register (ADC0_RDATA). Table 14-6.
Page 281: Routine Parallel Mode
GD32E502xx User Manual Routine parallel mode 14.5.2. The routine parallel mode is enabled by setting the SYNCM[3:0] bits in the ADC0_CTL0 register to 4b’0110. In the routine parallel mode. All of the ADCs convert the routine sequence parallelly at the selected external trigger of ADC0. The trigger is selected by configuring the ETSRC bit in the ADC_CTL1 register of ADC0.
Page 282: Routine Follow-Up Slow Mode
GD32E502xx User Manual Note: The maximum sampling time allowed is < 7 CK_ADC cycles to avoid the overlap between ADC0 and ADC1 sampling phases in the event that they convert the same channel. Figure 14-15. Routine follow-up fast mode on 1 channel in continuous operation mode Routine follow-up slow mode 14.5.4.
Page 283: Adc Interrupts
GD32E502xx User Manual ADC interrupts 14.6. The interrupt can be produced on one of the events:  End of conversion for routine sequence.  The analog watchdog 0/1 event. Separate interrupt enable bits are available for flexibility. The interrupts of ADC0 and ADC1 are mapped into the same interrupt vector IRQ18.
Page 284: Register Definition
GD32E502xx User Manual Register definition 14.7. ADC0 base address: 0x4001 2400 ADC1 base address: 0x4001 2800 Status register (ADC_STAT) 14.7.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved WDE1 Reserved rc_w0 Reserved STRC Reserved...
Page 285: Control Register 0 (Adc_Ctl0)
GD32E502xx User Manual 1: Analog w atchdog 0 event is happening Set by hardw are w hen the converted voltage crosses the values programmed in the ADC_WDLT0 and ADC_WDHT0 registers. Cleared by softw are writing 0 to it. Control register 0 (ADC_CTL0) 14.7.2.
Page 286 GD32E502xx User Manual Reserved Must be kept at reset value. DISRC Discontinuous mode on routine sequence 0: Discontinuous operation mode on routine sequence disable 1: Discontinuous operation mode on routine sequence enable Reserved Must be kept at reset value. WD0SC When in scan mode, analog w atchdog 0 is effective on a single channel.
Page 287: Control Register 1 (Adc_Ctl1)
GD32E502xx User Manual the temperature sensor, and to V inputs. REFINT ADC1 analog inputs Channel16, and Channel17 are internally connected to Control register 1 (ADC_CTL1) 14.7.3. Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved INREFEN TSVEN SWRCST Reserved ETERC Reserved...
Page 288: Sample Time Register 0 (Adc_Sampt0)
GD32E502xx User Manual 1: MSB alignment 10:9 Reserved Must be kept at reset value. DMA request enable 0: DMA request disable 1: DMA request enable Note: This bit is only used in ADC0. Reserved Must be kept at reset value. RSTCLB Reset calibration registers This bit is set by softw are and cleared by hardw are after the calibration registers...
Page 289: Sample Time Register 1 (Adc_Sampt1)
GD32E502xx User Manual Bits Fields Descriptions 31:24 Reserved Must be kept at reset value. 23:21 SPT17[2:0] Refer to SPT10[2:0] description 20:18 SPT16[2:0] Refer to SPT10[2:0] description 17:15 SPT15[2:0] Refer to SPT10[2:0] description 14:12 SPT14[2:0] Refer to SPT10[2:0] description 11:9 SPT13[2:0] Refer to SPT10[2:0] description SPT12[2:0] Refer to SPT10[2:0] description...
Page 290: Watchdog High Threshold Register 0 (Adc_Wdht0)
GD32E502xx User Manual 23:21 SPT7[2:0] Refer to SPT0[2:0] description 20:18 SPT6[2:0] Refer to SPT0[2:0] description 17:15 SPT5[2:0] Refer to SPT0[2:0] description 14:12 SPT4[2:0] Refer to SPT0[2:0] description 11:9 SPT3[2:0] Refer to SPT0[2:0] description SPT2[2:0] Refer to SPT0[2:0] description SPT1[2:0] Refer to SPT0[2:0] description SPT0[2:0] Channel sample time 000: Channel sampling time is 2.5 cycles...
Page 291: Routine Sequence Register 0 (Adc_Rsq0)
GD32E502xx User Manual This register has to be accessed by word (32-bit). Reserved Reserved WDLT0[11:0] Bits Fields Descriptions 31:12 Reserved Must be kept at reset value. 11:0 WDLT0[11:0] Low threshold for analog w atchdog 0 These bits define the low threshold for the analog w atchdog 0. Routine sequence register 0 (ADC_RSQ0) 14.7.8.
Page 292: Routine Sequence Register 2 (Adc_Rsq2)
GD32E502xx User Manual This register has to be accessed by word (32-bit). Reserved RSQ11[4:0] RSQ10[4:0] RSQ9[4:1] RSQ9[0] RSQ8[4:0] RSQ7[4:0] RSQ6[4:0] Bits Fields Descriptions 31:30 Reserved Must be kept at reset value. 29:25 RSQ11[4:0] Refer to RSQ0[4:0] description 24:20 RSQ10[4:0] Refer to RSQ0[4:0] description 19:15 RSQ9[4:0] Refer to RSQ0[4:0] description...
Page 293: Routine Data Register (Adc_Rdata)
GD32E502xx User Manual RSQ0[4:0] The channel number (0..17) is w ritten to these bits to select a channel as the nth conversion in the routine sequence. Routine data register (ADC_RDATA) 14.7.11. Address offset: 0x4C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). ADC1RDTR[15:0] RDATA[15:0] Bits...
Page 294 GD32E502xx User Manual 11: 6-bit 11:10 Reserved Must be kept at reset value. TOVS Triggered Oversampling This bit is set and cleared by softw are. 0: All oversampled conversions for a channel are done consecutively after a trigger. 1: Each conversion needs a trigger for an oversampled channel and the number of triggers is determined by the oversampling ratio (OVSR[2:0]).
Page 295: Watchdog 1 Channel Selection Register (Adc_Wd1Sr)
GD32E502xx User Manual Note: The softw are allow s this bit to be w ritten only w hen ADCON = 0 (this ensures that no conversion is in progress). Watchdog 1 channel selection register (ADC_WD1SR) 14.7.13. Address offset: 0xA0 Reset value: 0x00000000 This register has to be accessed by word (32-bit).
Page 296 GD32E502xx User Manual Bits Fields Descriptions 31:24 Reserved Must be kept at reset value. 23:16 WDHT1[7:0] High threshold for analog w atchdog 1 These bits define the high threshold for the analog w atchdog 1. Note: Softw are is allow ed to w rite these bits only w hen the ADC is disabled (ADCON =0).
Page 297: Digital-To-Analog Converter (Dac)
GD32E502xx User Manual Digital-to-analog converter (DAC) Overview 15.1. The Digital-to-analog converter converts 12-bit digital data to a voltage on the external pins. The digital data can be configured in 8-bit or 12-bit mode, left-aligned or right-aligned mode. DMA can be used to update the digital data on external triggers. The output voltage can be optionally buffered for higher drive capability.
Page 298: Function Overview
GD32E502xx User Manual Table 15-1. DAC I/O description Nam e Description Signal type Analog pow er supply Pow er Ground for analog pow er supply Pow er Reference voltage Analog input REF+ 2.7V ≤ V ≤ V REF+ DAC_OUT DAC analog output Analog output Note: The GPIO pins (PA7 for DAC_OUT) should be configured to analog mode before enable the DAC module.
Page 299: Dac Workflow
GD32E502xx User Manual DAC workflow 15.3.5. If the external trigger is enabled, the DAC holding data is transferred to the DAC output data (OUT_DO) register when the selected trigger event happened. When the external trigger is disabled, the transfer is performed automatically. When the DAC holding data is loaded into the OUT_DO register, after the time t , the SETTLING...
Page 300: Dac Output Calculate
GD32E502xx User Manual Figure 15-3. DAC triangle noise wave (2<<DWBWx)-1 DACx_DH value DAC output calculate 15.3.7. The analog output voltages on the DAC pin are determined by the following equation: *OUT_DO/4096 (15-1) DAC_out REF+ The digital input is linearly converted to an analog output voltage, its range is 0 to V REF+ DMA request 15.3.8.
Page 301: Registers Definition
GD32E502xx User Manual Registers definition 15.4. DAC base address: 0x4000 7400 Control register (DAC_CTL) 15.4.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved DDUDR DDMA Reserved DDISC DWBW[3:0] DWM[1:0] Reserved DTSEL[1:0] DTEN DBOFF Bits...
Page 302: Software Trigger Register (Dac_Swt)
GD32E502xx User Manual 0111: The bit w idth of the w ave signal is 8 1000: The bit w idth of the w ave signal is 9 1001: The bit w idth of the w ave signal is 10 1010: The bit w idth of the w ave signal is 11 ≥1011: The bit w idth of the w ave signal is 12 DWM[1:0] DAC_OUT noise w ave mode...
Page 303: Dac_Out 12-Bit Right-Aligned Data Holding Register (Out_R12Dh)
GD32E502xx User Manual Bits Fields Descriptions 31:1 Reserved Must be kept at reset value. SWTR DAC_OUT softw are trigger, cleared by hardw are. 0: Softw are trigger disabled 1: Softw are trigger enabled DAC_OUT 12-bit right-aligned data holding register (OUT_R12DH) 15.4.3.
Page 304: Dac_Out 8-Bit Right-Aligned Data Holding Register (Out_R8Dh)
GD32E502xx User Manual Reserved Must be kept at reset value. DAC_OUT 8-bit right-aligned data holding register (OUT_R8DH) 15.4.5. Address offset: 0x10 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved OUT_DH[7:0] Bits Fields Descriptions 31:8 Reserved Must be kept at reset value.
Page 305 GD32E502xx User Manual This register has to be accessed by word (32-bit). Reserved DDUDR Reserved Reserved rc_w1 Bits Fields Descriptions 31:14 Reserved Must be kept at reset value. DDUDR DAC_OUT DMA underrun flag, set by hardw are, cleared by softw are w rite 1. 0: No underrun occurred.
Page 306: Watchdog Timer (Wdgt)
GD32E502xx User Manual Watchdog timer (WDGT) The watchdog timer (WDGT) is a hardware timing circuitry that can be used to detect system failures due to software malfunctions. There are two watchdog timer peripherals in the chip: free watchdog timer (FWDGT) and window watchdog timer (WWDGT). They offer a combination of a high safety level, flexibility of use and timing accuracy.
Page 307: Figure 16-1. Free Watchdog Block Diagram
GD32E502xx User Manual Figure 16-1. Free watchdog block diagram The free watchdog is enabled by writing the value (0xCCCC) to the control register (FWDGT_CTL), then counter starts counting down. When the counter reaches the value (0x000), there will be a reset. The counter can be reloaded by writing the value (0xAAAA) to the FWDGT_CTL register at any time.
Page 308: Table 16-1. Min/Max Fwdgt Timeout Period At 40Khz (Irc40K)
GD32E502xx User Manual Table 16-1. Min/max FWDGT timeout period at 40KHz (IRC40K) Min tim eout (m s) RLD[11:0]= Max tim eout (m s) RLD[11:0]= Prescaler divider PSC[2:0] bits 0x000 0xFFF 1 / 4 0.025 409.525 1 / 8 0.025 819.025 1 / 16 0.025 1638.025...
Page 309: Register Definition
GD32E502xx User Manual Register definition 16.1.4. FWDGT base address: 0x4000 3000 Control register (FWDGT_CTL) Address offset: 0x00 Reset value: 0x0000 0000 This register can be accessed by half-word (16-bit) or word (32-bit). Reserved CMD[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 CMD[15:0] Write only.
Page 310 GD32E502xx User Manual FWDGT_STAT register is set and the value read from this register is invalid. 000: 1 / 4 001: 1 / 8 010: 1 / 16 011: 1 / 32 100: 1 / 64 101: 1 / 128 110: 1 / 256 111: 1 / 256 If several prescaler values are used by the application, it is mandatory to w ait until...
Page 311 GD32E502xx User Manual Reset value: 0x0000 0000 This register can be accessed by half-word (16-bit) or word (32-bit). Reserved Reserved Bits Fields Descriptions 31:3 Reserved Must be kept at reset value. Watchdog counter w indow value update When a w rite operation to FWDGT_WND register ongoing, this bit is set and the value read from FWDGT_WND register is invalid.
Page 312 GD32E502xx User Manual These bits are w rite protected. Write 0x5555 in the FWDGT_CTL register before w riting these bits. If several w indow values are used by the application, it is mandatory to w ait until WUD bit has been reset before changing the w indow value. How ever, after updating the w indow value it is not necessary to w ait until WUD is reset before continuing code execution except in case of low -pow er mode entry(Before entering low -power mode, it is necessary to w ait until WUD is reset).
Page 313: Window Watchdog Timer (Wwdgt)
GD32E502xx User Manual 16.2. Window watchdog timer (WWDGT) Overview 16.2.1. The window watchdog timer (WWDGT) is used to detect system failures due to software malfunctions. After the window watchdog timer starts, the value of down counter reduces progressively. The watchdog timer causes a reset when the counter reached 0x3F (the CNT[6] bit has been cleared).
Page 314: Figure 16-3. Window Watchdog Timing Diagram
GD32E502xx User Manual The window watchdog timer is always disabled after power on reset. The software starts the watchdog by setting the WDGTEN bit in the WWDGT_CTL register. When window watchdog timer is enabled, the counter counts down all the time, the configured value of the counter should be greater than 0x3F(it implies that the CNT[6] bit should be set).
Page 315: Table 16-2. Min-Max Timeout Value At 50 Mhz
GD32E502xx User Manual Table 16-2. Min-max timeout value at 50 MHz (f PCLK1 Min tim eout value Max tim eout value Prescaler divider PSC[1:0] CNT[6:0] =0x40 CNT[6:0]=0x7F 81.92 μs 1 / 1 5.24 ms 163.84 μs 1 / 2 10.49 ms 327.68 μs 1 / 4 20.97 ms...
Page 316: Register Definition
GD32E502xx User Manual Register definition 16.2.4. WWDGT base address: 0x4000 2C00 Control register (WWDGT_CTL) Address offset: 0x00 Reset value: 0x0000 007F This register can be accessed by half-word (16-bit) or word (32-bit). Reserved Reserved WDGTEN CNT[6:0] Bits Fields Descriptions 31:8 Reserved Must be kept at reset value.
Page 317 GD32E502xx User Manual WWDGTRST bit of the RCU module. A w rite operation of 0 has no effect. PSC[1:0] Prescaler. The time base of the w atchdog counter 00: (PCLK1 / 4096) / 1 01: (PCLK1 / 4096) / 2 10: (PCLK1 / 4096) / 4 11: (PCLK1 / 4096) / 8 WIN[6:0]...
Page 318: Real-Time Clock (Rtc)
GD32E502xx User Manual Real-time clock (RTC) Overview 17.1. The RTC is usually used as a clock-calendar. The RTC circuits are located in two power supply domains. The ones in the Backup Domain consist of a 32-bit up-counter, an alarm, a prescaler, a divider and the RTC clock configuration register.
Page 319: Rtc Reset
GD32E502xx User Manual (stored in the RTC_ALRMH/L register). Figure 17-1. Block diagram of RTC APB1 BUS PCLK1 APB interface RTC_Second SCIF HXTAL/128 SCIE RTC Interrupt RTCCLK RTC_Overflow SC_CLK LXTAL RTC_DIV RTC_CNT OVIF NVIC OVIE interrupt IRC40K RTC_Alarm Reload controler COMPARE ALRMIF RTC_PSC ALRMIE...
Page 320: Rtc Configuration
GD32E502xx User Manual RTC configuration 17.3.3. The RTC_PSC, RTC_CNT and RTC_ALRM registers in the RTC core are writable. These registers’ value can be set only when the peripheral enter configuration mode. And the CMF bit in the RTC_CTL register is used to indicate the configuration mode status. The write operation executes when the peripheral exit configuration mode, and it takes at least three RTCCLK cycles to complete.
Page 321: Figure 17-3. Rtc Second And Overflow Waveform Example (Rtc_Psc= 3)
GD32E502xx User Manual Figure 17-2. RTC second and alarm waveform example (RTC_PSC = 3, RTC_ALRM = 2) RTCCLK RTC_ PSC RTC_Second RTC _ CNT RTC_ Alarm ALRMIF ALRMIF flag can be cleared by software Figure 17-3. RTC second and overflow waveform example (RTC_PSC= 3) RTCCLK FFFFFFFD FFFFFFFE...
Page 322: Register Definition
GD32E502xx User Manual Register definition 17.4. RTC base address: 0x4000 2800 RTC interrupt enable register (RTC_INTEN) 17.4.1. Address offset: 0x00 Reset value: 0x0000 0000 This register can be accessed by half-word (16-bit) or word (32-bit). Reserved Reserved OVIE ALRMIE SCIE Bits Fields Descriptions...
Page 323: Rtc Prescaler High Register (Rtc_Psch)
GD32E502xx User Manual 31:6 Reserved Must be kept at reset value. LWOFF Last w rite operation finished flag 0: Last w rite operation on RTC registers did not finished. 1: Last w rite operation on RTC registers finished. Configuration mode flag 0: Exit configuration mode.
Page 324: Rtc Prescaler Low Register (Rtc_Pscl)
GD32E502xx User Manual PSC[19:16] RTC prescaler value high RTC prescaler low register (RTC_PSCL) 17.4.4. Address offset: 0x0C Reset value: 0x0000 8000 This register can be accessed by half-word (16-bit) or word (32-bit). Reserved PSC[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 PSC[15:0] RTC prescaler value low...
Page 325: Rtc Counter High Register (Rtc_Cnth)
GD32E502xx User Manual DIV[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 DIV[15:0] RTC divider value low The RTC divider register is reloaded by hardw are w hen the RTC prescaler or RTC counter register updated. RTC counter high register (RTC_CNTH) 17.4.7.
Page 326: Rtc Alarm High Register (Rtc_Alrmh)
GD32E502xx User Manual RTC alarm high register (RTC_ALRMH) 17.4.9. Address offset: 0x20 Reset value: 0x0000 FFFF This register can be accessed by half-word (16-bit) or word (32-bit). Reserved ALRM[31:16] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 ALRM[31:16] RTC alarm value high...
Page 327: Timer
GD32E502xx User Manual TIMER Table 18-1. Timers (TIMERx) are divided into three sorts TIMER TIMER0/7/19/20 TIMER1 TIMER5/6 TYPE Advanced General-L0 Basic Prescaler 16-bit 16-bit 16-bit Counter 16-bit 16-bit 16-bit Count m ode UP, DOWN, Center-aligned UP, DOWN, Center-aligned UP ONLY ●...
Page 328: Advanced Timer (Timerx, X=0, 7, 19, 20)
GD32E502xx User Manual 18.1. Advanced timer (TIMERx, x=0, 7, 19, 20) Overview 18.1.1. The advanced timer module (TIMER0/7/19/20) is a eight-channel timer that supports both input capture and output compare. They can generate PWM signals to control motor or be used for power management applications.
Page 329: Block Diagram
GD32E502xx User Manual Block diagram 18.1.3. Figure 18-1. Advanced timer block diagram provides details of the internal configuration of the advanced timer, and Table 18-2. Advanced timer channel description introduces the input and output of the channels. Figure 18-1. Advanced timer block diagram CH0_IN Input Logic CH1_IN...
Page 330: Figure 18-2. Timing Chart Of Internal Clock Divided By 1
GD32E502xx User Manual The default clock source is the CK_TIMER for driving the counter prescaler when the SMC[2:0] = 3’b000. When the CEN is set, the CK_TIMER will be divided by PSC value to generate PSC_CLK. In this mode, the TIMER_CK which drives counter’s prescaler to count is equal to CK_TIMER which is from RCU module.
Page 331: Figure 18-3. Timing Chart Of Psc Value Change From 0 To 2
GD32E502xx User Manual pulse on each ETI signal rising edge to clock the counter prescaler. Note: The ETI pin can select from TIMER_ETIx(x=0..2) pins, and each advanced TIMER only can use one of them. Plese refer to TIMER input source select register (SYSCFG_TIMERINSEL) for more details.
Page 332: Figure 18-4. Timing Chart Of Up Counting Mode, Psc=0/2
GD32E502xx User Manual If the UPDIS bit in TIMERx_CTL0 register is set, the update event is disabled. When an update event occurs, all the shadow registers (repetition counter register, counter auto reload register, prescaler register) are updated. Figure 18-4. Timing chart of up counting mode, PSC=0/2 Figure 18-5.
Page 333: Figure 18-5. Timing Chart Of Up Counting Mode, Change Timerx_Car On The Go
GD32E502xx User Manual Figure 18-5. Timing chart of up counting mode, change TIMERx_CAR on the go TIMER_CK PSC_CLK ARSE = 0 CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) Auto-reload register change CAR Vaule ARSE = 1 CNT_REG 114 115 116 117 118 119 120 Update event (UPE) Update interrupt flag (UPIF)
Page 334: Figure 18-6. Timing Chart Of Down Counting Mode, Psc=0/2
GD32E502xx User Manual the counter behavior in different clock frequencies when TIMERx_CAR = 0x 99. Figure 18-6. Timing chart of down counting mode, PSC=0/2 TIMER_CK PSC = 0 PSC_CLK CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) PSC = 2 PSC_CLK CNT_REG Update event (UPE)
Page 335 GD32E502xx User Manual Counter center-aligned counting In this mode, the counter counts up from 0 to the counter-reload value and then counts down to 0 alternatively. The Timer module generates an overflow event when the counter counts to the counter-reload value subtract 1 in the up-counting direction and generates an underflow event when the counter counts to 1 in the down-counting direction.
Page 336: Figure 18-8. Timing Chart Of Center-Aligned Counting Mode
GD32E502xx User Manual Figure 18-8. Timing chart of center-aligned counting mode TIMER_CK PSC_CLK CNT_REG Underflow Overflow UPIF CHxCV=2 TIMERx_CTL0 CAM = 2'b11 CHxIF TIMERx_CTL0 CAM = 2'b10 (upcount only CHxIF TIMERx_CTL0 CAM = 2'b10 (downcount only CHxIF Hardware set Software clear Update event (from overflow/underflow) rate configuration The rate of update events generation (from overflow and underflow events) can be configured by the TIMERx_CREP register.
Page 337: Figure 18-9. Repetition Counter Timing Chart Of Center-Aligned Counting Mode
GD32E502xx User Manual If an update event is generated by software after writing an odd number to CREP, the update events will be generated on the underflow. If the next update event occurs on overflow after writing an odd number to CREP, then the subsequent update events will be generated on the overflow.
Page 338: Figure 18-11. Repetition Counter Timing Chart Of Down Counting Mode
GD32E502xx User Manual Figure 18-11. Repetition counter timing chart of down counting mode TIMER_CK PSC_CLK CNT_REG Underflow Overflow TIMERx_CREP = 0x0 UPIF TIMERx_CREP = 0x1 UPIF TIMERx_CREP = 0x2 UPIF Input capture and output compare channels The advanced timer has eight independent channels which can be used as capture inputs or compare outputs.
Page 339: Figure 18-12. Channel 0 Input Capture Principle
GD32E502xx User Manual Figure 18-12. Channel 0 input capture principle Edge Detector Synchronizer Edge selector &inverter Based on Filter CH0P&MCH0P TIMER_CK CI0FE0 CI0FE0 Rising&Falling Rising/Falling Capture CI1FE0 Clock Prescaler Register Prescaler MCI0FE0 （CH0VAL） CH0IF CH0CAPPSC CH0_CC_I CH0IE CH0MS TIMERx_CC_INT Capture INT From Other Channals ITI0 ITI1 ITI2...
Page 340: Figure 18-14. Channel Output Compare Principle (When Mchxmsel = 2'00, X=0, 1, 2, 3)
GD32E502xx User Manual capture signal can also be selected from the input signal of other channel or the internal trigger signal by configuring CHxMS/ MCHxMS bits. The IC prescaler makes several input events generate one effective capture event. On the capture event, TIMERx_CHxCV/ TIMERx_MCHxCV will store the value of counter.
Page 341: Figure 18-16. Channel Output Compare Principle (With Complementary Output When Mchxmsel = 2'11, X=0,1,2,3)
GD32E502xx User Manual MCHxMSEL = 2’11, x=0,1,2,3) show the principle circuit of channels output compare function. Figure 18-14. Channel output compare principle (when MCHxMSEL = 2’00, x=0, 1, 2, 3) OxCPRE/MOxCPRE Capture/ CNT>CHxCV/ Compare register MCHxCV CHxCV/MCHxCV Compare output Output enable and CNT=CHxCV/ CHx_O control...
Page 342 GD32E502xx User Manual output level of CHx_O and MCHx_O depends on OxCPRE signal, CHxP bit and CHxEN bit.. It is invalid for the configuration of MCHx_O. Please refer to Figure 18-15. Channel output compare principle (when MCHxMSEL = 2’01, x=0, 1, 2, When MCHxMSEL=2’b11, the MCHx_O output is the inverse of the CHx_O output.
Page 343: Figure 18-17. Output-Compare Under Three Modes
GD32E502xx User Manual Figure 18-17. Output-compare under three modes shows the three compare modes: toggle/set/clear. CARL=0x63, CHxVAL=0x3. Figure 18-17. Output-compare under three modes CNT_CLK …. …. …. CNT_REG 03 04 03 04 03 04 Overflow match toggle OxCPRE match set OxCPRE match clear OxCPRE...
Page 344: Figure 18-18. Eapwm Timechart
GD32E502xx User Manual Figure 18-18. EAPWM timechart CARL CHxVAL OxCPRE OxCPRE CHxIF CHxOF Figure 18-19. CAPWM timechart CARL CHxVAL PWM MODE0 OxCPRE PWM MODE1 OxCPRE Interrupt signal CAM=2'b01 down only CHxIF CHxOF CAM=2'b10 up only CHxIF CHxOF CAM=2'b11 up/down CHxIF CHxOF Composite PWM mode In the Composite PWM mode (CHxCPWMEN = 1’b1, CHxMS[2:0] = 3’b000 and...
Page 345: Table 18-3.The Composite Pwm Pulse Width
GD32E502xx User Manual If CHxCOMCTL = 3’b111 (PWM mode 1) and DIR = 1’b0 (up counting mode), or CHxCOMCTL = 3’b110 (PWM mode 0) and DIR = 1’b1 (down counting mode) the channel x output is forced high when the counter matches the value of CHxVAL. It is forced low when the counter matches the value of CHxCOMVAL_ADD.
Page 346: Figure 18-20. Channel X Output Pwm With (Chxval < Chxcomval_Add)
GD32E502xx User Manual between 0 and CARL. Figure 18-20. Channel x output PWM with (CHxVAL < CHxCOMVAL_ADD) CARL CHxCOMVAL_ ADD=CARL CHxCOMVAL_ CHxVAL CHxVAL PWM MODE 1 PWM MODE 1 OxCPRE OxCPRE PWM MODE 0 PWM MODE 0 OxCPRE OxCPRE Interrupt signal Interrupt signal CHxIF CHxIF...
Page 347: Figure 18-23. Channel X Output Pwm With Chxval Or Chxcomval_Add Exceeds Carl
GD32E502xx User Manual CHxVAL = CARL CARL CHxVAL CHxCOMVAL_ADD CHxCOMVAL_ADD PWM MODE 1 PWM MODE 1 OxCPRE OxCPRE PWM MODE 0 PWM MODE 0 OxCPRE OxCPRE Interrupt signal Interrupt signal CHxIF CHxIF CHxCOMADDIF CHxCOMADDIF CARL CHxVAL CHxCOMVAL_ADD = 0 PWM MODE 1 OxCPRE PWM MODE 0 OxCPRE...
Page 348: Figure 18-25. Four Channels Outputs In Composite Pwm Mode
GD32E502xx User Manual next counter next counter period period If more than one channels are configured in composite PWM mode, it is possible to fix an offset for the channel x match edge of each pair with respect to other channels. This behavior is useful in the generation of lighting PWM control signals where it is desirable that edges are not coincident with each other pair to help eliminate noise generation.
Page 349: Figure 18-26. Chx_O Output With A Pulse In Edge -Aligned Mode (Chxompsel≠2'B00)
GD32E502xx User Manual CHxCOMCTL[2:0] bits;  CHxOMPSEL = 2’b01, only the counter is counting up, the OxCPRE signal is output a pulse when the match events occur, and the pulse width is one CK_TIMER clock cycle.  CHxOMPSEL = 2’b10, only the counter is counting down, the OxCPRE signal is output a pulse when the match events occur, and the pulse width is one CK_TIMER clock cycle.
Page 350 GD32E502xx User Manual Channel output prepare signal Figure 18-14. Channel output compare principle (when MCHxMSEL = 2’00, As is shown in x=0, 1, 2, 3) Figure 18-16. Channel output compare principle (with complementary output when MCHxMSEL = 2’11, x=0,1,2,3), when TIMERx is configured in compare match output mode, a middle signal named OxCPRE or MOxCPRE (channel x output or multi mode channel x output prepare signal) will be generated before the channel outputs signal.
Page 351: Table 18-4. Complementary Outputs Controlled By Parameters (Mchxmsel =2'B11)
GD32E502xx User Manual =2’b11)), ISOx and Complementary outputs controlled by parameters (MCHxMSEL ISOxN bits in the TIMERx_CTL1 register. The output polarity is determined by CHxP and MCHxP bits in the TIMERx_CHCTL2 register. Table 18-4. Complementary outputs controlled by parameters (MCHxMSEL =2’b11) Com plem entary Param eters Output Status POEN ROS...
Page 352: Figure 18-28. Channel Output Complementary Pwm With Dead-Time Insertion
GD32E502xx User Manual (4) ⊕: Xor calculate. (5) (!OxCPRE)：the complementary output of the OxCPRE signal. Insertion dead time for complementary PWM The dead time insertion is enabled when MCHxMSEL=2’b11 and both CHxEN and MCHxEN are configured to 1’b1, it is also necessary to configure POEN to 1. The field named DTCFG defines the dead time delay that can be used for all channels.
Page 353: Figure 18-29. Break Function Diagram
GD32E502xx User Manual independent control of dead-time insertion function for each pair of channels. When the DTIENCHx(x=0..3) bit is “0”, the corresponding channels CHx_O and CHx_ON will not be inserted into the dead-time. Break mode In this function, CHx_O and MCHx_O are controlled by the POEN, OAEN, IOS and ROS bits in the TIMERx_CCHP register, ISOx and ISOxN bits in the TIMERx_CTL1 register.
Page 354: Figure 18-30. Output Behavior Of The Channel In Response To A Break (The Break High Active)
GD32E502xx User Manual As soon as POEN is 0, the level of the CHx_O and MCHx_O outputs are determined by the ISOx and ISOxN bits in the TIMERx_CTL1 register. If IOS = 0, the timer releases the enable output, otherwise, the enable output remains high. The complementary outputs are first in the reset state, and then the dead time generator is reactivated to drive the outputs with the level programmed in the ISOx and ISOxN bits after a dead time.
Page 355: Figure 18-31. Counter Behavior With Ci0Fe0 Polarity Non-Inverted In Mode 2
GD32E502xx User Manual select whether each pair of channels uses the separated dead time insertion and break function. When the FCCHPyEN=0, the ROS、IOS and DTCFG[7:0] bits in TIMERx_CCHP register is active; When the FCCHPyEN=1, the ROS 、 IOS and DTCFG[7:0] bits in TIMERx_FCCHP0 register is active.
Page 356: Figure 18-32. Counter Behavior With Ci0Fe0 Polarity Inverted In Mode 2
GD32E502xx User Manual Figure 18-32. Counter behavior with CI0FE0 polarity inverted in mode 2 Hall sensor function Hall sensor is generally used to control BLDC motor, the timers can support this function. Figure 18-33. Hall sensor is used for BLDC motor shows how to connect the timer and the motor.
Page 357: Figure 18-33. Hall Sensor Is Used For Bldc Motor
GD32E502xx User Manual Figure 18-33. Hall sensor is used for BLDC motor TIMER_in Input capture GPIO Core TIMER_out Output compare PWM output Figure 18-34. Hall sensor timing between two timers Advanced/General L0 TIMER_in under input capture mode CH0_INPUT CH1_INPUT CH2_INPUT CI0(OXR) Counter CH0VAL...
Page 358: Figure 18-35. Restart Mode
GD32E502xx User Manual Master-slave management The TIMERx can be synchronized with a trigger in several modes including restart mode, pause mode and event mode which is selected by the SMC[2:0] bits in the TIMERx_SMCFG register. The input trigger of these modes can be selected by the TRGS[3:0] bits in the TIMERx_SMCFG register.
Page 359: Figure 18-36. Pause Mode
GD32E502xx User Manual Mode Selection Source Selection Polarity Selection Filter and Prescaler and it w ill start w hen event w ill occur on the the trigger input is rising edge only. high. Figure 18-36. Pause m ode TIMER_CK CNT_REG CI0FE0 TRGIF Event m ode...
Page 360: Figure 18-38. Single Pulse Mode Timerx_Chxcv=0X04, Timerx_Car=0X99
GD32E502xx User Manual update event occurs or the CEN bit is written to 0 by software. If the CEN bit is cleared to 0 by software, the counter will be stopped and its value will be held. In the single pulse mode, the active edge of trigger which sets the CEN bit to 1 will enable the counter.
Page 361: Figure 18-39. Timer0 Master/Slave Mode Example
GD32E502xx User Manual Figure 18-39. TIMER0 master/slave mode example TIMER0 TIMER 7 TRGS Master ITI0 TRGO Prescaler Counter mode control TIMER 1 Master TRGO ITI1 Prescaler Counter mode control TIMER 19 Master ITI2 TRGO Prescaler Counter mode control Trigger selection TIMER 20 Master TRGO...
Page 362: Figure 18-40. Triggering Timer0 With Enable Signal Of Timer1
GD32E502xx User Manual 1. Configure TIMER1 in master mode to send its enable signal as trigger output (MMC=3’b001 in the TIMER1_CTL1 register). 2. Select TIMER1 as TIMER0 input trigger source (TRGS=3’b010 in the TIMERx_SMCFG register). 3. Configure TIMER0 in event mode (SMC=3’b110 in TIMERx_SMCFG register). 4.
Page 363: Figure 18-41. Triggering Timer0 And Timer1 With Timer1'S Ci0 Input
GD32E502xx User Manual Figure 18-41. Triggering TIMER0 and TIMER1 with TIMER1’s CI0 input TIMER1 TIMER_CK TRGIF CNT_REG TIMER0 TRGIF CNT_CK CNT_REG Timer DMA mode Timer DMA mode is the function that configures timer’s register by DMA module. The relative registers are TIMERx_DMACFG and TIMERx_DMATB. Corresponding DMA request bit should be asserted to enable DMA request for internal interrupt event.
Page 364: Registers Definition (Timerx, X=0, 7, 19, 20)
GD32E502xx User Manual Registers definition (TIMERx, x=0, 7, 19, 20) 18.1.5. TIMER0 base address: 0x4001 2C00 TIMER7 base address: 0x4001 3400 TIMER19 base address: 0x4001 5000 TIMER20 base address: 0x4001 5400 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 365 GD32E502xx User Manual 11: Center-aligned and counting up/dow n assert mode. The counter counts in center-aligned mode and channel is configured in output mode (CHxMS = 3’b000 in TIMERx_CHCTL0 register). Both w hen counting up and counting dow n, the CHx F bit can be set.
Page 366 GD32E502xx User Manual Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved ISO3N ISO3 ISO2N ISO2 ISO1N ISO1 ISO0N ISO0 TI0S MMC[2:0] DMAS CCUC Reserved CCSE Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. ISO3N Idle state of multi mode channel 3 complementary output.
Page 367 GD32E502xx User Manual slave timers for synchronization function. 000: When a counter reset event occurs, a TRGO trigger signal is output. The counter resert source: Master timer generate a reset the UPG bit in the TIMERx_SWEV G register is set 001: Enable.
Page 368 GD32E502xx User Manual Slave mode configuration register (TIMERx_SMCFG) Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). TRGS[3] Reserved SMC1 ETPSC[1:0] ETFC[3:0] TRGS[2:0] Reserved SMC[2:0] Bits Fields Descriptions TRGS[3] Trigger selection. Refer to TRGS[2:0] description. 30:16 Reserved Must be kept at reset value.
Page 369 GD32E502xx User Manual filtering capability. Basic principle of digital filter: continuously sample the external trigger signal according to f and record the number of times of the same level of the signal. SAMP After reaching the filtering capacity configured by this bit-field, it is considered to be an effective level.
Page 370 GD32E502xx User Manual 1010：The filtered output of multi mode channel 0 input (MCI0FEM0) 1011：The filtered output of multi mode channel 1 input (MCI1FEM1) 1100：The filtered output of multi mode channel 2 input (MCI2FEM2) 1101：The filtered output of multi mode channel 3 input (MCI3FEM3) 1110：Reserved 1111：Reserved These bits must not be changed w hen slave mode is enabled.
Page 371 GD32E502xx User Manual Note: This bit just used in composite PWM mode (w hen CH3CPWMEN=1, CH3MS[2:0] = 3’b000 and CH3COMCTL=3’b110 or 3’b111). CH2COMADDIE Channel 2 additional compare interrupt enable 0: Disabled 1: Enabled Note: This bit just used in composite PWM mode (w hen CH2CPWMEN=1, CH2MS[2:0] = 3’b000 and CH2COMCTL=3’b110 or 3’b111).
Page 372 GD32E502xx User Manual Note: This bit just used for channel input and output independent mode (w hen MCH3MSEL[1:0] = 2b’00). MCH2IE Multi mode channel 2 capture/compare interrupt enable 0: Disabled 1: Enabled Note: This bit just used for channel input and output independent mode (w hen MCH2MSEL[1:0] = 2b’00).
Page 373 GD32E502xx User Manual 1: Enabled BRKIE Break interrupt enable 0: Disabled 1: Enabled TRGIE Trigger interrupt enable 0: Disabled 1: Enabled CMTIE Commutation interrupt enable 0: Disabled 1: Enabled CH3IE Channel 3 capture/compare interrupt enable 0: Disabled 1: Enabled CH2IE Channel 2 capture/compare interrupt enable 0: Disabled 1: Enabled...
Page 374 GD32E502xx User Manual Bits Fields Descriptions CH3COMADDIF Channel 3 additional compare interrupt flag. Refer to CH0COMA DDIF description. CH2COMADDIF Channel 2 additional compare interrupt flag. Refer to CH0COMA DDIF description. CH1COMADDIF Channel 1 additional compare interrupt flag. Refer to CH0COMA DDIF description. CH0COMADDIF Channel 0 additional compare interrupt flag.
Page 375 GD32E502xx User Manual TIMERx_MCH0CV. 0: No multi mode channel 0 capture/compare interrupt occurred 1: Multi mode channel 0 capture/compare interrupt occurred 19:13 Reserved Must be kept at reset value. CH3OF Channel 3 over capture flag Refer to CH0OF description CH2OF Channel 2 over capture flag Refer to CH0OF description CH1OF...
Page 376 GD32E502xx User Manual Refer to CH0IF description CH0IF Channel 0 capture/compare interrupt flag This flag is set by hardw are and cleared by softw are. If channel 0 is in input mode, this flag is set w hen a capture event occurs. If channel 0 is in output mode, this flag is set w hen a compare event occurs.
Page 377 GD32E502xx User Manual Note: This bit just used in composite PWM mode (w hen CH0CPWMEN=1, CH0MS[2:0] = 3’b000 and CH0COMCTL=3’b110 or 3’b111). 27:24 Reserved Must be kept at reset value. MCH3G Multi mode channel 3 capture or compare event generation. Refer to MCH0G description.
Page 378 GD32E502xx User Manual Refer to CH0G description CH2G Channel 2 capture or compare event generation Refer to CH0G description CH1G Channel 1 capture or compare event generation Refer to CH0G description CH0G Channel 0 capture or compare event generation This bit is set by softw are to generate a capture or compare event in channel 0, it is automatically cleared by hardw are.
Page 379 GD32E502xx User Manual Refer to CH1MS[1:0]description CH0MS[2] Channel 0 I/O mode selection Refer to CH0MS[1:0] description CH1COMADDSEN Channel 1 additional compare output shadow enable Refer to CH0COMA DDSEN description. CH0COMADDSEN Channel 0 additional compare output shadow enable When this bit is set, the shadow register of TIMERx_CH0COMV_ADD register w hich updates at each update event w ill be enabled.
Page 380 GD32E502xx User Manual 0: Channel 0 output compare clear disabled 1: Channel 0 output compare clear enabled CH0COMCTL[2:0] Channel 0 compare output control This bit-field controls the behavior of O0CPRE w hich drives CH0_O. The active level of O0CPRE is high, w hile the active level of CH0_O depends on CH0P bit. Note: When multi mode channel 0 is configured in output mode, and the MCH0MSEL[1:0] = 2b’11, This bit-field controls the behavior of O0CPRE w hich drives CH0_O and MCH0_O.
Page 381 GD32E502xx User Manual This bit cannot be modified w hen PROT[1:0] bit-field in TIMERx_CCHP register is 11 and CH0MS bit-field is 000. Reserved Must be kept at reset value. CH0MS[1:0] Channel 0 I/O mode selection This bit-field specifies the w ork mode of the channel and the input signal selection. The CH0MS[2:0] bit-field is w ritable only w hen the channel is not active (When MCH0MSEL[1:0] = 2b’00, the CH1EN bit in TIMERx_CHCTL2 register is reset;...
Page 382 GD32E502xx User Manual CH0CAPFLT [3:0] Tim es SAMP 4’b0000 Filter disabled. 4’b0001 4’b0010 CK_TIMER 4’b0011 4’b0100 4’b0101 4’b0110 4’b0111 4’b1000 4’b1001 4’b1010 4’b1011 4’b1100 4’b1101 4’b1110 4’b1111 CH0CAPPSC[1:0] Channel 0 input capture prescaler This bit-field specifies the factor of the prescaler on channel 0 input. The prescaler is reset w hen CH0EN bit in TIMERx_CHCTL2 register is cleared.
Page 383 GD32E502xx User Manual Output com pare m ode: Bits Fields Descriptions CH3MS[2] Channel 3 I/O mode selection Refer to CH3MS[1:0]description. CH2MS[2] Channel 2 I/O mode selection Refer to CH2MS[1:0] description. CH3COMADDSEN Channel 3 additional compare output shadow enable Refer to CH2COMA DDSEN description. CH2COMADDSEN Channel 2 additional compare output shadow enable When this bit is set, the shadow register of TIMERx_CH2COMV_ADD register...
Page 384 GD32E502xx User Manual CH2COMCEN Channel 2 output compare clear enable. When this bit is set, if the ETIFP signal is detected as high level, the O2CPRE signal w ill be cleared. 0: Channel 2 output compare clear disabled 1: Channel 2 output compare clear enabled CH2COMCTL[2:0] Channel 2 compare output control This bit-field specifies the compare output mode of the the output prepare signal...
Page 385 GD32E502xx User Manual CH2COMSEN Channel 2 compare output shadow enable When this bit is set, the shadow register of TIMERx_CH2CV register, w hich updates at each update event w ill be enabled. 0: Channel 2 output compare shadow disabled 1: Channel 2 output compare shadow enabled The PWM mode can be used w ithout verifying the shadow register only in single pulse mode (w hen SPM=1).
Page 386 GD32E502xx User Manual The CI2 input signal can be filtered by digital filter and this bit-field configure the filtering capability. Basic principle of digital filter: continuously sample the CI2 input signal according to and record the number of times of the same level of the signal. After reaching SAMP the filtering capacity configured by this bit, it is considered to be an effective level.
Page 387 GD32E502xx User Manual MCH3P MCH3EN CH3P CH3EN MCH2P MCH2EN CH2P CH2EN MCH1P MCH1EN CH1P CH1EN MCH0P MCH0EN CH0P CH0EN Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. MCH3P Multi mode channel 3 capture/compare polarity Refer to MCH0P description. MCH3EN Multi mode channel 3 capture/compare enable Refer to MCH0EN description.
Page 388 GD32E502xx User Manual 11 or 10. MCH0EN Multi mode channel 0 capture/compare enable When multi mode channel 0 is configured in output mode, setting this bit enables MCH0_O signal in active state. When multi mode channel 0 is configured in input mode, setting this bit enables the capture event in multi mode channel 0.
Page 389 GD32E502xx User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 CNT[15:0] This bit-field indicates the current counter value. Writing to this bit-field can change the value of the counter. Prescaler register (TIMERx_PSC) Address offset: 0x28 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 390 GD32E502xx User Manual Note: When the timer is configured in input capture mode, this register must be configured a non-zero value (such as 0xFFFF) w hich is larger than user expected value. Counter repetition register (TIMERx_CREP) Address offset: 0x30 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 391 GD32E502xx User Manual When channel 0 is configured in output mode, this bit-field contains value to be compared to the counter. When the corresponding shadow register is enabled, the shadow register updates by every update event. Channel 1 capture/compare value register (TIMERx_CH1CV) Address offset: 0x38 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 392 GD32E502xx User Manual at the last capture event. And this bit-field is read-only. When channel 2 is configured in output mode, this bit-field contains value to be compared to the counter. When the corresponding shadow register is enabled, the shadow register updates by every update event. Channel 3 capture/compare value register (TIMERx_CH3CV) Address offset: 0x40 Reset value: 0x0000 0000...
Page 393 GD32E502xx User Manual The bit can be set to 1 by: - Write 1 to this bit - If OAEN is set to 1, this bit is set to 1 at the next update event. The bit can be cleared to 0 by: - Write 0 to this bit - Valid fault input.
Page 394 GD32E502xx User Manual When POEN bit is reset (Idle mode), this bit can be set to enable the “off -state” for the channels w hich has been configured in output mode. Please refer to Table 18-4. Complementary outputs controlled by parameters ( M CHxM SEL =2’b11).
Page 395 GD32E502xx User Manual Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). MCH1 MCH0 Reserved MS[2] MS[2] MCH1CO MCH1CO MCH0CO MCH0CO MCH1COMCTL[2:0] Reserved MCH0COMCTL[2:0] Reserved MCEN MSEN MCEN MSEN MCH1MS[1:0] MCH0MS[1:0] MCH1CAPPSC MCH0CAPPSC MCH1CAPFLT[3:0] MCH0CAPFLT[3:0] [1:0] [1:0] Output com pare m ode: Bits...
Page 396 GD32E502xx User Manual 101~111: Reserved. MCH0COMCEN Multi mode channel 0 output compare clear enable. When this bit is set, if the ETIFP signal is detected as high level, the MO0CPR E signal w ill be cleared. 0: Multi mode channel 0 output compare clear disabled. 1: Multi mode channel 0 output compare clear enabled.
Page 397 GD32E502xx User Manual 0: Multi mode channel 0 output compare shadow disabled 1: Multi mode channel 0 output compare shadow enabled The PWM mode can be used w ithout verifying the shadow register only in single pulse mode (w hen SPM=1). This bit cannot be modified w hen PROT[1:0] bit-field in TIMERx_CCHP register is 11 and MCH0MS bit-field is 00.
Page 398 GD32E502xx User Manual reaching the filtering capacity configured by this bit, it is considered to be an effective level. The filtering capability configuration is as follow s: MCH0CA PFLT[3:0] Tim es SAMP 4’b0000 Filter disabled. 4’b0001 4’b0010 TIMER_CK 4’b0011 4’b0100 4’b0101 4’b0110 4’b0111...
Page 399 GD32E502xx User Manual MCH3CAPFLT[3:0] MCH3CAPPSC[1:0] MCH2CAPFLT[3:0] MCH2CAPPSC[1:0] Output com pare m ode: Bits Fields Descriptions MCH3MS[2] Multi mode channel 1 I/O mode selection Refer to MCH3MS[1:0]description. MCH2MS[2] Multi mode channel 0 I/O mode selection Refer to MCH2MS[1:0] description. 29:16 Reserved Must be kept at reset value.
Page 400 GD32E502xx User Manual Note: When multi mode channel 2 is configured in output mode, and the MCH2MSEL[1:0] = 2b’11, the CH2COMCTL[2:0] bit-field controls the behavior of O2CPRE w hich drives CH2_O and MCH2_O, w hile the active level of CH2_O and MCH2_O depends on CH2P and MCH2P bits.
Page 401 GD32E502xx User Manual 000: Multi mode channel 2 is programmed as output. 001: Multi mode channel 2 is programmed as input, MIS2 is connected to MCI2FEM2. 010: Multi mode channel 2 is programmed as input, MIS2 is connected to MCI3FEM2. 011: Multi mode channel 2 is programmed as input, MIS2 is connected to ITS.
Page 402 GD32E502xx User Manual 4’b0111 4’b1000 4’b1001 4’b1010 4’b1011 4’b1100 4’b1101 4’b1110 4’b1111 MCH2CA PPSC[1:0] Multi mode channel 2 input capture prescaler. This bit-field specifies the factor of the prescaler on channel 2 input. The prescaler is reset w hen MCH2EN bit in TIMERx_CHCTL2 register is cleared. 00: Prescaler disable, capture occurs on every active edge of the input signal 01: The capture input prescaler factor is 2.
Page 403 GD32E502xx User Manual When multi mode channel 0 is configured in output mode, and the MCH0MSEL[ 1:0] = 2b’00, these bits specifie the multi mode channel 0 output signal polarity. 00: Multi mode channel 0 active high 01: Multi mode channel 0 active low 10: Reserved.
Page 404 GD32E502xx User Manual Multi mode channel 1 capture/compare value register (TIMERx_MCH1CV) Address offset: 0x58 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved MCH1VAL[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 MCH1VAL[15:0] Capture/compare value of multi mode channel 1.
Page 405 GD32E502xx User Manual Multi mode channel 3 capture/compare value register (TIMERx_MCH3CV) Address offset: 0x60 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved MCH3VAL[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 MCH3VAL[15:0] Capture/compare value of channel 3.
Page 406 GD32E502xx User Manual Channel 1 additional compare value register (TIMERx_CH1COMV_ADD) Address offset: 0x68 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved CH1COMVAL_ADD[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 CH1COMVAL_ADD Additional compare value of channel 1 [15:0]...
Page 407 GD32E502xx User Manual Channel 3 additional compare value register (TIMERx_CH3COMV_ADD) Address offset: 0x70 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved CH3COMVAL_ADD[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 CH3COMVAL_ADD Additional compare value of channel 3 [15:0]...
Page 408 GD32E502xx User Manual CH1CPWMEN Channel 1 composite PWM mode enable 0: Disabled 1: Enabled CH0CPWMEN Channel 0 composite PWM mode enable 0: Disabled 1: Enabled 27:26 MCH3MSEL[1:0] Multi mode channel 3 mode select 00: Independent mode, MCH3 is independent of CH3 01: Mirrored mode, just used for output, the MCH3 output is the same as CH3 output 10: Reserved 11: Complementary mode, only the CH3 is valid for input, and the outputs of MCH3...
Page 409 GD32E502xx User Manual 11: Both the counter is counting up and counting dow n, the O3CPRE signal is output a pulse w hen the match events occur, and the pulse w idth is one CK_TIMER clock cycle. 13:12 CH2OMPSEL[1:0] Channel 2 output match pulse select When the match events occurs, this bit is used to select the output of O2CPRE w hich drives CH2_O.
Page 410 GD32E502xx User Manual BRKENCH3 Break control enable for channel 3 0: Disabled 1: Enabled BRKENCH2 Break control enable for channel 2 0: Disabled 1: Enabled BRKENCH1 Break control enable for channel 1 0: Disabled 1: Enabled BRKENCH0 Break control enable for channel 0 0: Disabled 1: Enabled DTIENCH3...
Page 411 GD32E502xx User Manual Bits Fields Descriptions BRK3P BRKIN3 input signal polarity This bit specifies the polarity of the BRKIN3 input signal. 0: BRKIN3 input active low 1: BRKIN3 input active high This bit can be modified only w hen PROT[1:0] bit-field in TIMERx_CCHP register is BRK3EN BRKIN3 input signal enable This bit can be set to enable the BRKIN3 input.
Page 412 GD32E502xx User Manual 0: BRKIN0 input active low 1: BRKIN0 input active high This bit can be modified only w hen PROT[1:0] bit-field in TIMERx_CCHP register is BRK0EN BRKIN0 input signal enable This bit can be set to enable the BRKIN0 input. 0: Break inputs disabled 1: Break inputs enabled This bit can be modified only w hen PROT[1:0] bit-field in TIMERx_CCHP register is...
Page 413 GD32E502xx User Manual 0101: f /2, N=8 SAMP 0110: f /4, N=6 SAMP 0111: f /4, N=8 SAMP 1000: f /8, N=6 SAMP 1001: f /8, N=8 SAMP 1010: f /16, N=5 SAMP 1011: f /16, N=6 SAMP 1100: f /16, N=8 SAMP 1101: f...
Page 414 GD32E502xx User Manual 0100: f /2, N=6 SAMP 0101: f /2, N=8 SAMP 0110: f /4, N=6 SAMP 0111: f /4, N=8 SAMP 1000: f /8, N=6 SAMP 1001: f /8, N=8 SAMP 1010: f /16, N=5 SAMP 1011: f /16, N=6 SAMP 1100: f...
Page 415 GD32E502xx User Manual enabled, w ith relationship to CH0EN/MCH0EN bits in TIMERx_CHCTL2 register. This bit cannot be modified w hen PROT [1:0] bit-filed in TIMERx_CCHP register is 10 or 11. Idle mode off-state configure When POEN bit is reset, this bit specifies the output state for the channels w hich has been configured in output mode.
Page 416 GD32E502xx User Manual 1: the ROS、IOS and DTCFG[7:0] bits in TIMERx_FCCHP1 register is active This bit can be modified only w hen PROT [1:0] bit-filed in TIMERx_CCHP register is 00. 30:12 Reserved Must be kept at reset value. Run mode off-state configure When POEN bit is set, this bit specifies the output state for the channels w hich has a complementary output and has been configured in output mode.
Page 417 GD32E502xx User Manual FCCHP2 Reserved Reserved Reserved DTCFG[7:0] Bits Fields Descriptions FCCHP2EN Free complementary channel protection register 2 enable 0: the ROS、IOS and DTCFG[7:0] bits in TIMERx_CCHP register is active 1: the ROS、IOS and DTCFG[7:0] bits in TIMERx_FCCHP2 register is active This bit can be modified only w hen PROT [1:0] bit-filed in TIMERx_CCHP register is 00.
Page 418 GD32E502xx User Manual DTCFG [7:5] =3’b111: DTvalue = (32+DTCFG [4:0])xt *16. This bit can be modified only w hen PROT [1:0] bit-filed in TIMERx_CCHP register is 00. Free complementary channel protection register 3 (TIMERx_FCCHP3) Address offset: 0x88 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 419 GD32E502xx User Manual This bit cannot be modified w hen PROT [1:0] bit-filed in TIMERx_CCHP register is 10 or 11. Reserved Must be kept at reset value. DTCFG[7:0] Dead time configure This bit-field controls the value of the dead-time, w hich is inserted before the output transitions.
Page 420 GD32E502xx User Manual DMA transfer buffer register (TIMERx_DMATB) Address offset: 0xE4 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved DMATB[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 DMATB[15:0] DMA transfer buffer When a read or w rite operation is assigned to this register, the register located at the address ranges from (start address) to (start address + transfer count * 4) w il l be accessed.
Page 421 GD32E502xx User Manual This bit-field is set and reset by softw are. 1: If POEN bit and IOS bit are 0, the output is disabled. 0: No effect.
Page 422: General Level0 Timer (Timerx, X=1)
GD32E502xx User Manual 18.2. General level0 timer (TIMERx, x=1) Overview 18.2.1. The general level0 timer module (TIMER1) is a four-channel timer that supports input capture and output compare. They can generate PWM signals to control motor or be used for power management applications.
Page 423: Function Overview
GD32E502xx User Manual Figure 18-42. General Level 0 timer block diagram CH0_IN Input Logic CH1_IN Synchronizer&Filter Edge selector Prescaler CH2_IN &Edge Detector CH3_IN ITI0 ITI1 ITI2 ITI3 TIMERx_CHxCV CK_TIMER Counter External Trigger Input logic Trigger processor PSC_CLK Polarity selection TIMER_CK Trigger Selector&Counter Edge detector ETIFP...
Page 424: Figure 18-43. Timing Chart Of Internal Clock Divided By 1
GD32E502xx User Manual Figure 18-43. Timing chart of internal clock divided by 1 CK_TIMER update event generate(UPG) Reload Pulse Update event (UPE) PSC_CLK = TIMER_CK CNT_REG SMC[2:0] = 3’b111 (external clock mode 0). External input pin is selected as timer clock ...
Page 425: Figure 18-44. Timing Chart Of Psc Value Change From 0 To 2
GD32E502xx User Manual Figure 18-44. Timing chart of PSC value change from 0 to 2 TIMER_CK PSC value Prescaler shadow Prescaler CNT PSC_CLK CNT_REG Reload Pulse Counter up counting In this mode, the counter counts up continuously from 0 to the counter-reload value, which is defined in the TIMERx_CAR register, in a count-up direction.
Page 426: Figure 18-45. Timing Chart Of Up Counting Mode, Psc=0/2
GD32E502xx User Manual Figure 18-45. Timing chart of up counting mode, PSC=0/2 TIMER_CK PSC = 0 PSC_CLK CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) PSC = 2 PSC_CLK CNT_REG Update event (UPE) Software clear Update interrupt flag (UPIF) Hardware set Figure 18-46.
Page 427: Figure 18-47. Timing Chart Of Down Counting Mode, Psc=0/2
GD32E502xx User Manual Counter down counting In this mode, the counter counts down continuously from the counter-reload value, which is defined in the TIMERx_CAR register, to 0 in a count-down direction. Once the counter reaches to 0, the counter will start counting down from the counter-reload value. The update event is generated at each counter underflow.
Page 428: Figure 18-48. Timing Chart Of Down Counting Mode, Change Timerx_Car On The Go
GD32E502xx User Manual Figure 18-48. Timing chart of down counting mode, change TIMERx_CAR on the go TIMER_CK PSC_CLK ARSE = 0 CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) Auto-reload register change CAR Vaule ARSE = 1 CNT_REG 119 118 Update event (UPE) Update interrupt flag (UPIF)
Page 429: Figure 18-49. Timing Chart Of Center-Aligned Counting Mode
GD32E502xx User Manual Figure 18-49. Timing chart of center-aligned counting mode shows the example of the counter behavior when TIMERx_CAR=0x99, TIMERx_PSC=0x0. Figure 18-49. Timing chart of center-aligned counting mode TIMER_CK PSC_CLK CNT_REG Underflow Overflow UPIF CHxCV=2 TIMERx_CTL0 CAM = 2'b11 CHxIF TIMERx_CTL0 CAM = 2'b10 (upcount only CHxIF...
Page 430: Figure 18-50. Channels Input Capture Principle
GD32E502xx User Manual generated if it is enabled when CHxIE=1. Figure 18-50. Channels input capture principle Edge Detector Synchronizer Edge selector &inverter Based on CH0P&CH0NP TIMER_CK CI0FE0 CI0FE0 Rising/Falling Rising&Falling Capture Clock CI1FE0 Register Prescaler Prescaler （CH0VAL） CH0IF CH0CAPPSC CH0IE CH0MS TIMERx_CC_INT ITI0...
Page 431: Figure 18-51. Channel Output Compare Principle (X=0,1,2,3)
GD32E502xx User Manual The channel input capture function can be also used for pulse width measurement from signals on the TIMERx_CHx pins. For example, PWM signal connects to CI0 input. Select CI0 as channel 0 capture signals by setting CH0MS to 2’b01 in the channel control register (TIMERx_CHCTL0) and set capture on rising edge.
Page 432: Figure 18-52. Output-Compare Under Three Modes
GD32E502xx User Manual Step3: Interrupt/DMA-request enables configuration by CHxIE/CHxDEN. Step4: Compare output timing configuration by TIMERx_CAR and TIMERx_CHxCV. The TIMERx_CHxCV can be changed onging to meet the expected waveform. Step5: Start the counter by configuring CEN to 1. Figure 18-52. Output-compare under three modes shows the three compare modes toggle/set/clear.
Page 433: Figure 18-53. Eapwm Timechart
GD32E502xx User Manual TIMERx_CAR, the output will be always active in PWM mode 0 (CHxCOMCTL=3’b110). And if the value of TIMERx_CHxCV is greater than the value of TIMERx_CAR, the output will be always inactive in PWM mode 1 (CHxCOMCTL=3’b111). Figure 18-53. EAPWM timechart CHxVAL PWM MODE0 Cx OUT...
Page 434: Table 18-7. Counting Direction In Different Quadrature Decoder Mode
GD32E502xx User Manual setting to low by configuring the CHxCOMCTL field to 0x02 or toggling signal by configuring the CHxCOMCTL field to 0x03 when the counter value matches the content of the TIMERx_CHxCV register. The PWM mode 0/PWM mode 1 output is another output type of OxCPRE which is setup by configuring the CHxCOMCTL field to 0x06/0x07.
Page 435: Figure 18-55. Counter Behavior With Ci0Fe0 Polarity Non-Inverted In Mode 2
GD32E502xx User Manual Figure 18-55. Counter behavior with CI0FE0 polarity non-inverted in mode 2 Figure 18-56. Counter behavior with CI0FE0 polarity inverted in mode 2 Hall sensor function Refer to Advanced timer (TIMERx, x=0, 7, 19, 20)Hall sensor function. Master-slave management The TIMERx can be synchronized with a trigger in several modes including restart mode, pause mode and event mode which is selected by the SMC[2:0] bits in the TIMERx_SMCFG register.
Page 436: Figure 18-57. Restart Mode
GD32E502xx User Manual Mode Selection Source Selection Polarity Selection Filter and Prescaler 101: CI0FE0 If ETIFP (the filtered prescaler can be used. 110: CI1FE1 output external For the ETIFP, filter can 111: ETIFP trigger input ETI) be used by configuring selected as the trigger ETFC prescaler...
Page 437: Figure 18-59. Event Mode
GD32E502xx User Manual Mode Selection Source Selection Polarity Selection Filter and Prescaler The counter w ill start ETIFP is selected. ETI does not change. divided by 2. to count w hen a rising ETFC = 0, ETI does not edge of trigger input filter.
Page 438: Figure 18-60. Single Pulse Mode Timerx_Chxcv = 0X04, Timerx_Car=0X99
GD32E502xx User Manual Figure 18-60. Single pulse mode TIMERx_CHxCV = 0x04, TIMERx_CAR=0x99 Timers interconnection Refer to Advanced timer (TIMERx, x=0, 7, 19, 20)Timers interconnection. Timer DMA mode Timer DMA mode is the function that configures timer’s register by DMA module. The relative registers are TIMERx_DMACFG and TIMERx_DMATB.
Page 439: Registers Definition (Timerx, X=1)
GD32E502xx User Manual Registers definition (TIMERx, x=1) 18.2.5. TIMER1 base address: 0x4000 0000 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register can be accessed by half-word (16-bit) or word (32-bit). Reserved Reserved CKDIV[1:0] ARSE CAM[1:0] UPDIS Bits Fields...
Page 440 GD32E502xx User Manual After the counter is enabled, these bits cannot be sw itched from 0x00 to non 0x00. Direction 0: Count up 1: Count dow n If the timer w ork in center-aligned mode or decoder mode, this bit is read only. Single pulse mode 0: Single pulse mode is disabled.
Page 441 GD32E502xx User Manual Reserved Reserved TI0S MMC[2:0] DMAS Reserved Bits Fields Descriptions 31:8 Reserved Must be kept at reset value. TI0S Channel 0 trigger input selection 0: The TIMERx_CH0 pin input is selected as channel 0 trigger input. 1: The result of combinational XOR of TIMERx_CH0, TIMERx_CH1 TIMERx_CH2 pins is selected as channel 0 trigger input.
Page 442 GD32E502xx User Manual Reserved Must be kept at reset value. Slave mode configuration register (TIMERx_SMCFG) Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved SMC1 ETPSC[1:0] ETFC[3:0] TRGS[2:0] Reserved SMC[2:0] Bits Fields Descriptions 31:16 Reserved...
Page 443 GD32E502xx User Manual filtering capability. Basic principle of digital filter: continuously sample the external trigger signal according to f and record the number of times of the same level of the signal. SAMP After reaching the filtering capacity configured by this bit-field, it is considered to be an effective level.
Page 444 GD32E502xx User Manual Reserved Must be kept at reset value. SMC[2:0] Slave mode control 000: Disable slave mode. The slave mode is disabled; The prescaler is clocked directly by the internal clock (TIMER_CK) w hen CEN bit is set high. 001: Quadrature decoder mode 0.
Page 445 GD32E502xx User Manual 0: Disabled 1: Enabled CH1DEN Channel 1 capture/compare DMA request enable 0: Disabled 1: Enabled CH0DEN Channel 0 capture/compare DMA request enable 0: Disabled 1: Enabled UPDEN Update DMA request enable 0: Disabled 1: Enabled Reserved Must be kept at reset value. TRGIE Trigger interrupt enable 0: Disabled...
Page 446 GD32E502xx User Manual Reserved Reserved CH3OF CH2OF CH1OF CH0OF Reserved TRGIF Reserved CH3IF CH2IF CH1IF CH0IF UPIF rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 Bits Fields Descriptions 31:13 Reserved Must be kept at reset value. CH3OF Channel 3 over capture flag Refer to CH0OF description CH2OF Channel 2 over capture flag...
Page 447 GD32E502xx User Manual 0 is in output mode, this flag is set w hen a compare event occurs. If channel 0 is set to input mode, this bit w ill be reset by reading TIMERx_CH0CV. 0: No channel 0 interrupt occurred 1: Channel 0 interrupt occurred UPIF Update interrupt flag...
Page 448 GD32E502xx User Manual and the corresponding interrupt or DMA request w ill be sent if enabled. In addition, if channel 0 is configured in input mode, the current value of the counter is captured to TIMERx_CH0CV register, and the CH0OF flag is set if the CH0IF flag has been set.
Page 449 GD32E502xx User Manual 00: Channel 1 is programmed as output. 01: Channel 1 is programmed as input, IS1 is connected to CI1FE1. 10: Channel 1 is programmed as input, IS1 is connected to CI0FE1. 11: Channel 1 is programmed as input, IS1 is connected to ITS. This mode is w orking only if an internal trigger input is selected (through TRGS bits in TIMERx_SMCFG register).
Page 450 GD32E502xx User Manual Reserved Must be kept at reset value. CH0MS[1:0] Channel 0 I/O mode selection This bit-field specifies the w ork mode of the channel and the input signal selection. This bit-field is w ritable only w hen the channel is not active (CH0EN bit in TIMERx_CHCTL2 register is reset).
Page 451 GD32E502xx User Manual 4’b1011 4’b1100 4’b1101 4’b1110 4’b1111 CH0CAPPSC[1:0] Channel 0 input capture prescaler This bit-field specifies the factor of the prescaler on channel 0 input. The prescaler is reset w hen CH0EN bit in TIMERx_CHCTL2 register is cleared. 00: Prescaler disabled, input capture occurs on every channel input edge. 01: The input capture occurs on every 2 channel input edges 10: The input capture occurs on every 4 channel input edges 11: The input capture occurs on every 8 channel input edges...
Page 452 GD32E502xx User Manual This bit-field is w ritable only w hen the channel is not active (CH3EN bit in TIMERx_CHCTL2 register is reset). 00: Channel 3 is programmed as output. 01: Channel 3 is programmed as input, IS3 is connected to CI3FE3. 10: Channel 3 is programmed as input, IS3 is connected to CI2FE3.
Page 453 GD32E502xx User Manual 1: Channel 2 output compare shadow enabled The PWM mode can be used w ithout verifying the shadow register only in single pulse mode (w hen SPM=1). Reserved Must be kept at reset value. CH2MS[1:0] Channel 2 I/O mode selection This bit-field specifies the w ork mode of the channel and the input signal selection.
Page 454 GD32E502xx User Manual 4’b1000 4’b1001 4’b1010 4’b1011 4’b1100 4’b1101 4’b1110 4’b1111 CH2CAPPSC[1:0] Channel 2 input capture prescaler This bit-field specifies the factor of the prescaler on channel 2 input. The prescaler is reset w hen CH2EN bit in TIMERx_CHCTL2 register is cleared. 00: Prescaler disabled, input capture occurs on every channel input edge.
Page 455 GD32E502xx User Manual CH2NP Channel 2 complementary capture/compare polarity Refer to CH0NP description. Reserved Must be kept at reset value. CH2P Channel 2 capture/compare function polarity Refer to CH0P description CH2EN Channel 2 capture/compare function enable Refer to CH0EN description CH1NP Channel 1 complementary capture/compare polarity Refer to CH0NP description.
Page 456 GD32E502xx User Manual 11 or 10. CH0EN Channel 0 capture/compare function enable When channel 0 is configured in output mode, setting this bit enables CH0_O signal in active state. When channel 0 is configured in input mode, setting this bit enables the capture event in channel0.
Page 457 GD32E502xx User Manual The TIMER_CK clock is divided by (PSC+1) to generate the counter clock. The value of this bit-field w ill be loaded to the corresponding shadow register at every update event. Counter auto reload register (TIMERx_CAR) Address offset: 0x2C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 458 GD32E502xx User Manual When channel 0 is configured in output mode, this bit-field contains value to be compared to the counter. When the corresponding shadow register is enabled, the shadow register updates by every update event. Channel 1 capture/compare value register (TIMERx_CH1CV) Address offset: 0x38 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 459 GD32E502xx User Manual at the last capture event. And this bit-field is read-only. When channel 2 is configured in output mode, this bit-field contains value to be compared to the counter. When the corresponding shadow register is enabled, the shadow register updates by every update event. Channel 3 capture/compare value register (TIMERx_CH3CV) Address offset: 0x40 Reset value: 0x0000 0000...
Page 460 GD32E502xx User Manual This filed defines the number(n) of the register that DMA w ill access(R/W), n = (DMATC [4:0] +1). DMATC [4:0] is from 5’b00000 to 5’b10001. Reserved Must be kept at reset value. DMATA[4:0] DMA transfer access start address This field define the first address for the DMA access the TIMERx_DMA TB.
Page 461 GD32E502xx User Manual Bits Fields Descriptions 31:2 Reserved Must be kept at reset value. CI0_RMP[1:0] Channel 0 input remap 00: Channel 0 input is connected to GPIO(TIMER1_CH0) 01: Channel 0 input is connected to the LXTAL 10: Channel 0 input is connected to HXTAL/128 clock 11: Channel 0 input is connected to CKOUT0SEL.
Page 462: Basic Timer (Timerx, X=5, 6)
GD32E502xx User Manual 18.3. Basic timer (TIMERx, x=5, 6) Overview 18.3.1. The basic timer module (TIMER5/6) has a 16-bit counter that can be used as an unsigned counter. The basic timer can be configured to generate a DMA request and a TRGO to connect to DAC.
Page 463: Figure 18-62. Timing Chart Of Internal Clock Divided By 1
GD32E502xx User Manual Figure 18-62. Timing chart of internal clock divided by 1 CK_TIMER update event generate(UPG) Reload Pulse Update event (UPE) PSC_CLK = TIMER_CK CNT_REG Clock prescaler The counter clock (PSC_CK) is obtained by the TIMER_CK through the prescaler, and the prescale factor can be configured from 1 to 65536 through the prescaler register (TIMERx_PSC).
Page 464: Figure 18-64. Timing Chart Of Up Counting Mode, Psc=0/2
GD32E502xx User Manual Counter up counting In this mode, the counter counts up continuously from 0 to the counter reload value, which is defined in the TIMERx_CAR register, in a count-up direction. Once the counter reaches the counter reload value, the counter will start counting up from 0 again. The update event is generated at each counter overflow.
Page 465: Figure 18-65. Timing Chart Of Up Counting Mode, Change Timerx_Car On The Go
GD32E502xx User Manual Figure 18-65. Timing chart of up counting mode, change TIMERx_CAR on the go TIMER_CK PSC_CLK ARSE = 0 CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) Auto-reload register change CAR Vaule ARSE = 1 CNT_REG 114 115 116 117 118 119 120 Update event (UPE) Update interrupt flag (UPIF)
Page 466: Registers Definition (Timerx, X=5, 6)
GD32E502xx User Manual Registers definition (TIMERx, x=5, 6) 18.3.5. TIMER5 base address: 0x4000 1000 TIMER6 base address: 0x4000 1400 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved ARSE Reserved...
Page 467 GD32E502xx User Manual – The UPG bit is set – The counter generates an overflow or underflow event – The restart mode generates an update event. 1: Update event disable. Note: When this bit is set to 1, setting UPG bit or the restart mode does not generate an update event, but the counter and prescaler are initialized.
Page 468 GD32E502xx User Manual Interrupt enable register (TIMERx_DMAINTEN) Address offset: 0x0C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved UPDEN Reserved UPIE Bits Fields Descriptions 31:9 Reserved Must be kept at reset value. UPDEN Update DMA request enable 0: Disabled 1: Enabled...
Page 469 GD32E502xx User Manual Software event generation register (TIMERx_SWEVG) Address offset: 0x14 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved Bits Fields Descriptions 31:1 Reserved Must be kept at reset value. This bit can be set by softw are, and automatically cleared by hardw are. When this bit is set, the counter is cleared.
Page 470 GD32E502xx User Manual Reserved PSC[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 PSC[15:0] Prescaler value of the counter clock The TIMER_CK clock is divided by (PSC+1) to generate the counter clock. The value of this bit-field w ill be loaded to the corresponding shadow register at every update event.
Page 471: Universal Synchronous/Asynchronous Receiver /Transmitter (Usart)
GD32E502xx User Manual Universal synchronous/asynchronous receiver /transmitter (USART) 19.1. Overview The Universal Synchronous/Asynchronous Receiver/Transmitter (USART) provides a flexible serial data exchange interface. Data frames can be transferred in full duplex or half duplex mode, synchronously or asynchronously through this interface. A programmable baud rate generator divides the UCLK (PCLK, CK_SYS, LXTAL or IRC16M) to produces a dedicated wide range baudrate clock for the USART transmitter and receiver.
Page 472: Function Overview
GD32E502xx User Manual – Transmits parity bit – Checks parity of received data byte  LIN Break generation and detection  IrDA Support  Synchronous mode and transmitter clock output for synchronous transmission  ISO 7816-3 compliant smartcard interface – Character mode (T=0) –...
Page 473: Usart Frame Format
GD32E502xx User Manual Type Description Output I/O (single- Transmit Data. High level When enabled but w ire/smartcard mode) nothing to be transmitted Output Serial clock for synchronous communication nCTS Input Clear to send in Hardw are flow control mode nRTS Output Request to send in Hardw are flow control mode Figure 19-1.
Page 474: Baud Rate Generation
GD32E502xx User Manual bits in the USART_CTL1 register. Table 19-2. Configuration of stop bits STB[1:0] stop bit length (bit) usage description Default value Smartcard mode for receiving Normal USART and single-w ire modes Smartcard mode for transmitting and receiving In an idle frame, all the frame bits are logic 1. The frame length is equal to the normal USART frame.
Page 475: Usart Transmitter
GD32E502xx User Manual USART transmitter 19.3.3. If the transmit enable bit (TEN) in USART_CTL0 register is set, when the transmit data buffer is not empty, the transmitter shifts out the transmit data frame through the TX pin. The polarity of the TX pin can be configured by the TINV bit in the USART_CTL1 register. Clock pulses can output through the CK pin.
Page 476: Usart Receiver
GD32E502xx User Manual It is necessary to wait for the TC bit to be asserted before disabling the USART or entering the power saving mode. This bit can be cleared by set the TCC bit in USART_INTC register. The break frame is sent when the SBKCMD bit is set, and SBKCMD bit is reset after the transmission.
Page 477: Use Dma For Data Buffer Access
GD32E502xx User Manual Figure 19-4. Oversampling method of a receive frame bit (OSB=0) If the parity check function is enabled by setting the PCEN bit in the USART_CTL0 register, the receiver calculates the expected parity value while receiving a frame. The received parity bit will be compared with this expected value.
Page 478: Figure 19-5. Configuration Step When Using Dma For Usart Transmission
GD32E502xx User Manual Configuration step when using DMA for USART transmission. Figure 19-5. Configuration step when using DMA for USART transmission Clear the TC bit in USART_STAT Set the address of USART_TDATA as the DMA destination address Set the address of data in internal sram as the DMA source address Set the number of data as the DMA transfer number...
Page 479: Hardware Flow Control
GD32E502xx User Manual Figure 19-6. Configuration step when using DMA for USART reception Set the address of USART_RDATA as the DMA source address Set the address of the buffer in internal sram as the DMA destination address Set the number of data as the DMA transfer number Set other configurations of DMA, interrupt enable, priority, etc...
Page 480: Multi-Processor Communication
GD32E502xx User Manual RTS flow control The USART receiver outputs the nRTS, which reflects the status of the receive buffer. When data frame is received, the nRTS signal goes high to prevent the transmitter from sending next frame. The nRTS signal keeps high when the receive buffer is full. CTS flow control The USART transmitter monitors the nCTS input pin to decide whether a data frame can be transmitted.
Page 481: Lin Mode
GD32E502xx User Manual The idle frame wake up method is selected by default. If the RWU bit is reset, an idle frame is detected on the RX pin, the IDLEF bit in USART_STAT will be set. If the RWU bit is set, an idle frame is detected on the RX pin, the hardware clears the RWU bit and exits the mute mode.
Page 482: Synchronous Mode
GD32E502xx User Manual frame can be selected by configuring LBLEN in USART_CTL1. When the RX pin is detected at low state for a time that is equal to or longer than the expected break frame length (10 bits when LBLEN=0, or 11 bits when LBLEN=1), the LBDF bit in USART_STAT is set. An interrupt occurs if the LBDIE bit in USART_CTL1 is set.
Page 483: Irda Sir Endec Mode
GD32E502xx User Manual Figure 19-11. Example of USART in synchronous mode Figure 19-12. 8-bit format USART synchronous waveform (CLEN=1) IrDA SIR ENDEC mode 19.3.10. The IrDA mode is enabled by setting the IREN bit in USART_CTL2. The LMEN, STB[1:0], CKEN bits in USART_CTL1 and HDEN, SCEN bits in USART_CTL2 should be cleared in IrDA mode.
Page 484: Figure 19-13. Irda Sir Endec Module
GD32E502xx User Manual Figure 19-13. IrDA SIR ENDEC module Inside chip Outside chip RX pin Receive Decoder Infrared Normal IREN USART TX pin Transmit Encoder SIR MODULE In IrDA mode, the polarity of the TX and RX pins is different. The TX pin is usually at low state, while the RX pin is usually at high state.
Page 485: Half-Duplex Communication Mode
GD32E502xx User Manual Half-duplex communication mode 19.3.11. The half-duplex communication mode is enabled by setting the HDEN bit in USART_CTL2. The LMEN, CKEN bits in USART_CTL1 and SCEN, IREN bits in USART_CTL2 should be cleared in half-duplex communication mode. Only one wire is used in half-duplex mode. The TX and RX pins are connected together internally.
Page 486 GD32E502xx User Manual During USART transmission, if a parity error event is detected, the smartcard may NACK the current frame by pulling down the TX pin during the last 1 bit time of the stop bits. The USART can automatically resend data according to the protocol for SCRTNUM times. An interframe gap of 2.5 bits time will be inserted before the start of a resented frame.
Page 487 GD32E502xx User Manual programming the BL value. However, before the start of the block, the maximum value of BL (0xFF) may be programmed. The real value will be programmed after the reception of the third character. The total block length (including prologue, epilogue and information fields) equals BL+4. The end of the block is signaled to the software through the EBF flag and interrupt (when EBIE bit is set).
Page 488: Figure 19-16. Usart Receive Fifo Structure
GD32E502xx User Manual Figure 19-16. USART Receive FIFO structure If the software read receive data buffer in the routing of the RBNE interrupt, the RBNEIE bit should be reset at the beginning of the routing and set after all of the receive data is read out. The PERR/NERR/FERR/EBF flags should be cleared before reading a receive data out.
Page 489 GD32E502xx User Manual Interrupt event Event flag Enable Control bit Transmission complete TCIE Received data ready to be RBNE read RBNEIE Overrun error detected ORERR Receive FIFO full RFFINT RFFIE Idle line detected IDLEF IDLEIE Parity error flag PERR PERRIE Break detected flag in LIN LBDF LBDIE...
Page 490: Figure 19-17. Usart Interrupt Mapping Diagram
GD32E502xx User Manual Figure 19-17. USART interrupt mapping diagram RFFINT RFFIE IDLEF IDLEIE RBNE RBNEIE ORERR RBNEIE PERR PERRIE FERR NERR ERRIE ORERR LBDF LBDIE USART_INT AMIE RTIE EBIE WUIE TCIE TBEIE CTSF CTSIE...
Page 491 GD32E502xx User Manual 19.4. Register definition USART0 base address: 0x4001 3800 USART1 base address: 0x4000 4400 USART2 base address: 0x4000 4800 Control register 0 (USART_CTL0) 19.4.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved EBIE RTIE...
Page 492 GD32E502xx User Manual expressed in sample time units (1/8 or 1/16 bit time), w hich are configured by the OVSMOD bit. This bit field cannot be w ritten w hen the USART is enabled (UEN=1). OVSMOD Oversample mode. 0: Oversampling by 16. 1: Oversampling by 8.
Page 493 GD32E502xx User Manual 1: Transmission complete interrupt is enabled. RBNEIE Read data buffer not empty interrupt and overrun error interrupt enable. 0: Read data register not empty interrupt and overrun error interrupt disabled. 1: An interrupt w ill occur w henever the ORERR bit is set or the RBNE bit is set in USART_STAT.
Page 494 GD32E502xx User Manual When WM[1:0] = 01, if the ADDM bit is reset, only the ADDR[3:0] bits are used to compare. In normal reception, these bits are also used for character detection. The w hole received character (8-bit) is compared to the ADDR[7:0] value and AMF flag is set on matching.
Page 495 GD32E502xx User Manual 11: 1.5 Stop bit. This bit field cannot be w ritten w hen the USART is enabled (UEN=1). CKEN CK pin enable. 0: CK pin disabled. 1: CK pin enabled. This bit field cannot be w ritten w hen the USART is enabled (UEN=1). Clock polarity.
Page 496 GD32E502xx User Manual Control register 2 (USART_CTL2) 19.4.3. Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved WUIE WUM[1:0] SCRTNUM[2:0] Reserved DDRE OVRD CTSIE CTSEN RTSEN DENT DENR SCEN NKEN HDEN IRLP IREN ERRIE Bits...
Page 497 GD32E502xx User Manual 1: DE signal is active low . This bit field cannot be w ritten w hen the USART is enabled (UEN=1). Driver enable mode. This bit is used to activate the external transceiver control, through the DE signal, w hich is output on the RTS pin.
Page 498 GD32E502xx User Manual This bit field cannot be w ritten w hen the USART is enabled (UEN=1). DENT DMA enable for transmission. 0: DMA mode is disabled for transmission. 1: DMA mode is enabled for transmission. DENR DMA enable for reception. 0: DMA mode is disabled for reception.
Page 499 GD32E502xx User Manual Reserved BRR [15:4] BRR[3:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:4 BRR[15:4] Integer of baud-rate divider. INTDIV = BRR[15:4]. BRR [3:0] Fraction of baud-rate divider. If OVSMOD = 0, FRADIV = BRR[3:0]. If OVSMOD = 1, FRADIV = BRR[2:0], BRR[3] must be reset.
Page 500 GD32E502xx User Manual factor is tw ice as the prescaler value. 00000: Reserved - do not program this value. 00001: divides the source clock by 2. 00010: divides the source clock by 4. 00011: divides the source clock by 6. This bit field cannot be w ritten w hen the USART is enabled (UEN=1).
Page 501 GD32E502xx User Manual Command register (USART_CMD) 19.4.7. Address offset: 0x18 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved Reserved TXFCMD RXFCMD MMCMD SBKCMD Reserved Bits Fields Descriptions 31:5 Reserved Must be kept at reset value. TXFCMD Transmit data flush request Writing 1 to this bit sets the TBE flag, to discard the transmit data.
Page 502 GD32E502xx User Manual 31:23 Reserved Must be kept at reset value. Receive enable acknow ledge flag. This bit, w hich is set/reset by hardw are, reflects the receive enable state of the USART core logic. 0: The USART core receiving logic has not been enabled. 1: The USART core receiving logic has been enabled.
Page 503 GD32E502xx User Manual 0: USART reception path is idle. 1: USART reception path is w orking. 15:13 Reserved Must be kept at reset value. End of block flag. 0: End of Block not reached. 1: End of Block (number of characters) reached. An interrupt is generated if the EBIE=1 in the USART_CTL1 register.
Page 504 GD32E502xx User Manual USART_CMD register. Cleared by a w rite to the USART_TDA TA. Transmission completed. 0: Transmission is not completed. 1: Transmission is complete. An interrupt w ill occur if the TCIE bit is set in USART_CTL0. Set by hardw are if the transmission of a frame containing data is completed and if the TBE bit is set.
Page 505 GD32E502xx User Manual an interrupt w ill occur if the ERRIE bit is set in USART_CTL2. Set by hardw are w hen a de-synchronization, excessive noise or a break character is detected. This bit w ill be set w hen the maximum number of transmit attempts is reached w ithout success (the card NACKs the data frame), w hen USART transmits in smartcard mode.
Page 506 GD32E502xx User Manual CTSC CTS change clear. Writing 1 to this bit clears the CTSF bit in the USART_STAT register. LBDC LIN break detected clear. Writing 1 to this bit clears the LBDF flag in the USART_STAT register. Reserved Must be kept at reset value. Transmission complete clear.
Page 507 GD32E502xx User Manual USART_CTL0 register). Transmit data register (USART_TDATA) 19.4.11. Address offset: 0x28 Reset value: Undefined This register has to be accessed by word (32-bit). Reserved Reserved TDATA[8:0] Bits Fields Descriptions 31:9 Reserved Must be kept at reset value. TDATA[8:0] Transmit Data value.
Page 508 GD32E502xx User Manual 1: Parity error is detected. Reserved Forced by hardw are to 0. Hardw are flow control coherence mode. 0: nRTS signal equals to the RBNE in status register. 1: nRTS signal is set w hen the last data bit (parity bit w hen pce is set) has been sampled.
Page 509 GD32E502xx User Manual The NACK pulse occurs 1/16 bit time earlier w hen the parity error is detected. 0:Early NACKdisable w hen smartcard mode is selected. 1:Early NACKenable w hen smartcard mode is selected.
Page 510: Figure 20-1. I2C Module Block Diagram
GD32E502xx User Manual Inter-integrated circuit interface (I2C) 20.1. Overview The I2C (inter-integrated circuit) module provides an I2C interface which is an industry standard two-line serial interface for MCU to communicate with external I2C interface. I2C bus uses two serial lines: a serial data line (SDA) and a serial clock line (SCL). The I2C interface implements standard I2C protocol with standard mode, fast mode and fast mode plus as well as CRC calculation and checking, SMBus (system management bus), and PMBus (power management bus).
Page 511: Table 20-1. Definition Of I2C-Bus Terminology (Refer To The I2C Specification Of Philips Semiconductors)
GD32E502xx User Manual Figure 20-1. I2C module block diagram PEC register SDA Controller CRC Calculation / Analog Digital Check Noise Noise filter filter Receive Data Register Shift Register Transmit SCL Controller Data Analog Digital Register Noise Noise filter filter Control Registers SMBA Timing and Control Logic...
Page 512: Figure 20-2. Data Validation
GD32E502xx User Manual Analog filter delay is maximum 260ns. Digital filter delay is DNF[3:0]×t I2CCLK The period of PCLK clock t match the conditions as follows: PCLK  <4/3*t PCLK with: : the period of SCL Note: When the I2C kernel is provided by PCLK, this clock must match the conditions for I2CCLK I2C communication flow 20.3.2.
Page 513: Figure 20-3. Start And Stop Signal
GD32E502xx User Manual Figure 20-3. START and STOP signal Each I2C device is recognized by a unique address (whether it is a microcontroller, LCD driver, memory or keyboard interface) and can operate as either a transmitter or receiver, depending on the function of the device. It operates in slave mode by default. When it generates a START signal, the interface automatically switches from slave to master.
Page 514: Figure 20-5. I2C Communication Flow With 7-Bit Address (Master Transmit)
GD32E502xx User Manual Figure 20-5. I2C communication flow with 7-bit address (Master Transmit) Figure 20-6. I2C communication flow with 7-bit address (Master Receive) In 10-bit addressing mode, the HEAD10R bit can configured to decide whether the complete address sequence must be executed, or only the header to be sent. When HEAD10R=0, the complete 10 bit address read sequence must be excuted with START + header of 10-bit address in write direction + slave address byte 2 + RESTART + header of 10-bit address in read direction, as is shown in...
Page 515: Figure 20-9. Data Hold Time
GD32E502xx User Manual Noise filter 20.3.3. Analog noise filter and digital noise filter are integrated in I2C peripherals, the noise filters can be configured before the I2C peripheral is enabled according to the actual requirements. The analog noise filter is disabled by setting the ANOFF bit in I2C_CTL0 register and enabled when ANOFF is 0.
Page 516: Figure 20-10. Data Setup Time
GD32E502xx User Manual Figure 20-10. Data setup time SU;DAT When the SCL falling edge is internally detected, a delay is inserted before sending SDA output. This delay is t = SDADELY * t where t = (PSC+1) * t SDADELY I2CCLK I2CCLK SDADELY...
Page 517: Table 20-2. Data Setup Time And Data Hold Time
GD32E502xx User Manual Table 20-2. Data setup time and data hold time Standard Fast m ode Fast m ode SMBus Sym bol Param eter m ode plus Unit Data hold time HD;DAT Data valid time 3.45 0.45 VD;DAT Data setup time SU;DAT Rising time of 1000...
Page 518: Figure 20-11. Data Transmission
GD32E502xx User Manual Figure 20-11. Data transmission SCL Stretch Shift register write data1 write data2 data0 data1 data2 I2C_TDATA Data Reception When receiving data, the data will be received in the shift register first. If RBNE is 0, the data in the shift register will move into I2C_RDATA register.
Page 519 GD32E502xx User Manual Working m ode Action Slave receiver mode ACK control SMBus mode PEC generation/checking The number of bytes to be transferred is configured by BYTENUM[7:0] in I2C_CTL1 register. If BYTENUM is greater than 255, or in slave byte control mode, the reload mode must be enabled by setting the RELOAD bit in I2C_CTL1 register.
Page 520 GD32E502xx User Manual low if necessary. The SCL will be stretched in following cases. The SCL is stretched when the ADDSEND bit is set, and released when the ADDSEND  bit is cleared. In slave transmitting mode, after the ADDSEND bit is cleared, the SCL will be stretched ...
Page 521: Figure 20-13. I2C Initialization In Slave Mode
GD32E502xx User Manual 1. I2CEN=0. 2. The slave has not been addressed. 3. ADDSEND=1. Only when the ADDSEND=1, or TCR=1, the RELOAD bit can be modified. Figure 20-13. I2C initialization in slave mode START I2CEN=0 Configure DNF[3:0] in I2C_CTL0 Configure PSC[3:0], SDADELY[3:0], SCLDELY[3:0] in I2C_TIMING Configure SS in I2C_CTL0 I2CEN=1...
Page 522: Figure 20-14. Programming Model For Slave Transmitting When Ss=0
GD32E502xx User Manual When SBCTL is 0, if ADDSEND=1, and the TBE bit in I2C_STAT register is 0, the data in I2C_TDATA register can be chosed to be transmitted or flushed. The data is flushed by setting the TBE bit. When SBCTL=1, the slave works in slave byte control mode, the BYTENUM[7:0] must be configured in the ADDSEND interrupt service routine.
Page 523: Figure 20-15. Programming Model For Slave Transmitting When Ss=1
GD32E502xx User Manual Figure 20-15. Programming model for slave transmitting when SS=1 I2C Line State Hardware Action Software Flow I2C initialization IDLE Set TBE Write DATA(1) to I2C_TDATA Master generates START condition Master sends Address read READDR and TR in Set ADDSEND Slave sends Acknowledge I2C_STAT, clear ADDSEND...
Page 524: Figure 20-16. Programming Model For Slave Receiving
GD32E502xx User Manual Figure 20-16. Programming model for slave receiving I2C Line State Hardware Action Software Flow IDLE Master generates START Software initialization condition Master sends Address Slave sends Acknowledge read READDR and TR in Set ADDSEND I2C_STAT, clear ADDSEND SCL stretched by slave (only when SS=0) Master sends DATA(1)
Page 525: Figure 20-17. I2C Initialization In Master Mode
GD32E502xx User Manual configured in I2C_CTL1 register. When the addressing mode is 10-bit in master receiving mode, the HEAD10R bit must be configured to decide whether the complete address sequence must be executed, or only the header to be sent. The number of bytes to be transferred should be configured in BYTENUM[7:0] in I2C_CTL1 register.
Page 526: Figure 20-18. Programming Model For Master Transmitting (N<=255)
GD32E502xx User Manual If data of BYTENUM[7:0] bytes have been transferred and RELOAD=0, the AUTOEND  bit in I2C_CTL1 can be set to generate a STOP signalautomatically. When AUTOEND is 0, the TC bit in I2C_STAT register will be set and the SCL is stretched. In this case, the master can generate a STOP signalby setting the STOP bit in the I2C_CTL1 register.
Page 527: Figure 20-19. Programming Model For Master Transmitting (N>255)
GD32E502xx User Manual Figure 20-19. Programming model for master transmitting (N>255) I2C Line State Hardware Action Software Flow Software initialization RELOAD =1 IDLE BYTENUM[7:0]=0xFF Master generates START N=N-255 condition Set START Master sends Address Slave sends Acknowledge Write DATA(1) to Set TI I2C_TDATA Wait for ACK from slave...
Page 528: Figure 20-20. Programming Model For Master Receiving (N<=255)
GD32E502xx User Manual Figure 20-20. Programming model for master receiving (N<=255) I2C Line State Hardware Action Software Flow Software initialization AUTOEND=0 BYTENUM[7:0]=N IDLE Set START START Condition Master sends Address Slave sends Acknowledge Slave sends DATA(1) Master sends Acknowledge Set RBNE Read DATA(1) （Data transmission）...
Page 529: Figure 20-21. Programming Model For Master Receiving (N>255)
GD32E502xx User Manual Figure 20-21. Programming model for master receiving (N>255) I2C Line State Hardware Action Software Flow Software initialization RELOAD =1 BYTENUM[7:0]=0xFF N=N-255 IDLE Set START START Condition Master sends Address Slave sends Acknowledge Slave sends DATA(1) Master sends Acknowledge Set RBNE Read DATA(1) （Data transmission）...
Page 530 GD32E502xx User Manual Configuration and Power Management Interface (abbreviated to ACPI) specifications. Address resolution protocol The SMBus uses I2C hardware and I2C hardware addressing, but adds second-level software for building special systems. Additionally, its specifications include an Address Resolution Protocol that can make dynamic address allocations. Dynamic reconfiguration of the hardware and software allow bus devices to be ‘hot-plugged’...
Page 531: Table 20-4. Smbus With Pec Configuration
GD32E502xx User Manual (BUSTOA+1)*2048*t , the TIMEOUT flag will be set in I2C_STAT register. I2CCLK The BUSTOB[11:0] is used to check the t of the slave and the t of the LOW:SEXT LOW:MEXT master. The timer can be enabled by setting the EXTOEN bit in the I2C_TIMEOUT register, after the EXTOEN bit is set, the BUSTOB[11:0] cannot be changed.
Page 532 GD32E502xx User Manual Bus idle detection If the master detects that the high level duration of the clock and data signals is greater than , the bus can be considered idle. HIGH,MAX This timing parameter includes the case of a master that has been dynamically added to the bus and may not have detected a state transition on a SMBCLK or SMBDAT lines.
Page 533: Figure 20-22. Smbus Master Transmitter And Slave Receiver Communication Flow
GD32E502xx User Manual must be set. In order to check the PEC byte, it is necessary to clear the RELOAD bit and set PECTRANS bit. After receiving BYTENUM-1 data, the next received byte will be compared with the data in the I2C_PEC register. If the PEC values does not match, the NACK is automatically generated.
Page 534: Table 20-5. I2C Error Flags
GD32E502xx User Manual Use DMA for data transfer 20.3.11. As is shown in I2C slave mode and I2C master mode, each time TI or RBNE is asserted, software should write or read a byte, this may cause CPU’s high overload. The DMA controller can be used to process TI and RBNE flag: each time TI or RBNE is asserted, DMA controller does a read or write operation automatically.
Page 535 GD32E502xx User Manual I2C debug mode 20.3.13. When the microcontroller enters the debug mode (Cortex®-M33 core halted), the SMBus timeout either continues to work normally or stops, depending on the I2Cx_HOLD configuration bits in the DBG module.
Page 536 GD32E502xx User Manual 20.4. Register definition I2C0 base address: 0x4000 5400 I2C1 base address: 0x4000 5800 Control register 0 (I2C_CTL0) 20.4.1. Address offset: 0x00 Reset value: 0x0000 0000 This register can be accessed by word (32-bit). SMBALT SMBDAE SMBHAE Reserved PECEN GCEN Reserved...
Page 537 GD32E502xx User Manual 1: Slave w ill response to a General Call Reserved Must be kept at reset value. Whether to stretch SCL low w hen data is not ready in slave mode. This bit is set and cleared by softw are. 0: SCL Stretching is enabled 1: SCL Stretching is disabled Note: When in master mode, this bit must be 0.
Page 538 GD32E502xx User Manual STPDETIE Stop detection interrupt enable 0: Stop detection (STPDET) interrupt is disabled 1: Stop detection (STPDET) interrupt is enabled NACKIE Not acknow ledge received interrupt enable 0: NACK received interrupt is disabled 1: NACK received interrupt is enabled ADDMIE Address match interrupt enable in slave mode 0: Address match interrupt is disabled...
Page 539 GD32E502xx User Manual 0: Don’t transfer PEC value 1: Transfer PEC Note: This bit has no effect w hen RELOAD=1, or SBCTL=0 in slave mode. AUTOEND Automatic end mode in master mode 0: TC bit is set w hen the transfer of BYTENUM[7:0] bytes is completed. 1: a STOP signal is sent automatically w hen the transfer of BYTENUM[7:0] bytes is completed.
Page 540 GD32E502xx User Manual (w rite) + slave address byte 2 + RESTART + header of 10-bit address (read). 1: The 10 bit master receive address sequence is RESTART + header of 10-bit address (read). Note: When the START bit is set, this bit can not be changed. ADD10EN 10-bit addressing mode enable in master mode 0: 7-bit addressing in master mode...
Page 541 GD32E502xx User Manual ADDRESSEN I2C address enable 0: I2C address disable. 1: I2C address enable. 14:11 Reserved Must be kept at reset value. ADDFORMAT Address mode for the I2C slave 0: 7-bit address 1: 10-bit address Note: When ADDRESSEN is set, this bit should not be w ritten. ADDRESS[1:0] Highest tw o bits of a 10-bit address Note: When ADDRESSEN is set, this bit should not be w ritten.
Page 542 GD32E502xx User Manual 111: ADDRESS2[7:1] are masked. All 7-bit received addresses are acknow ledged except the reserved address (0b0000xxx and 0b1111xxx). Note: When ADDRESS2EN is set, these bits should not be w ritten. If ADDMSK2 is not equal to 0, the reserved I2C addresses (0b0000xxx and 0b1111xxx) are not acknow ledged even if all the bits are matched.
Page 543 GD32E502xx User Manual =(SCLH+1)* t SCLH Note: These bits can only be used in master mode. SCLL[7:0] SCL low period SCL low period can be generated by configuring these bits. =(SCLL+1)*t SCLL Note: These bits can only be used in master mode. Timeout register (I2C_TIMEOUT) 20.4.6.
Page 544 GD32E502xx User Manual 0: BUSTOA is used to detect SCL low timeout 1: BUSTOA is used to detect both SCL and SDA high timeout w hen the bus is idle Note: This bit can be w ritten only w hen TOEN =0. 11:0 BUSTOA[11:0] Bus timeout A...
Page 545 GD32E502xx User Manual setting the SMBALTC bit. This bit is cleared by hardw are w hen I2CEN=0. 0: SMBALERT event is not detected on SMBA pin 1: SMBALERT event is detected on SMBA pin TIMEOUT TIMEOUT flag. When a timeout or extended clock timeout occurred, this bit w ill be set. It is cleared by softw are by setting the TIMEOUTC bit and cleared by hardw are w hen I2CEN=0.
Page 546 GD32E502xx User Manual BYTENUM[7:0] bytes have been transferred. It is cleared by softw are w hen START bit or STOP bit is set. 0: Transfer of BYTENUM[7:0] bytes is not completed 1: Transfer of BYTENUM[7:0] bytes is completed STPDET STOP signal detected in slave mode This flag is set by hardw are w hen a STOP signal is detected on the bus.
Page 547 GD32E502xx User Manual Status clear register (I2C_STATC) 20.4.8. Address offset: 0x1C Reset value: 0x0000 0000 This register can be accessed by word (32-bit). Reserved SMBALT TIMEOUT PECERR LOSTAR STPDET ADDSEN Reserved OUERRC BERRC Reserved NACKC Reserved Bits Fields Descriptions 31:14 Reserved Must be kept at reset value.
Page 548 GD32E502xx User Manual PEC register (I2C_PEC) 20.4.9. Address offset: 0x20 Reset value: 0x0000 0000 This register can be accessed by word (32-bit). Reserved Reserved PECV[7:0] Bits Fields Descriptions 31:8 Reserved Must be kept at reset value. PECV[7:0] Packet Error Checking Value that calculated by hardw are w hen PEC is enabled. PECV is cleared by hardw are w hen I2CEN = 0.
Page 549 GD32E502xx User Manual Reserved TDATA [7:0] Bits Fields Descriptions 31:8 Reserved Must be kept at reset value. TDATA[7:0] Transmit data value Control register 2 (I2C_CTL2) 20.4.12. Address offset: 0x90 Reset value: 0x0000 FE00 This register can be accessed by word (32-bit). Reserved ADDM[6:0] Reserved...
Page 550 GD32E502xx User Manual Serial peripheral interface/Inter-IC sound (SPI/I2S) Overview 21.1. The SPI/I2S module can communicate with external devices using the SPI protocol or the I2S audio protocol. The serial peripheral interface (SPI) provides a SPI protocol of data transmission and reception function in master or slave mode.
Page 551: Figure 21-1. Block Diagram Of Spi
GD32E502xx User Manual 21.3. SPI function overview SPI block diagram 21.3.1. Figure 21-1. Block diagram of SPI SYSCLK MOSI TX Buffer MISO RX Buffer SPI signal description 21.3.2. Normal configuration (not Quad-SPI mode) Table 21-1. SPI signal description Pin nam e Direction Description Master: SPI clock output...
Page 552: Figure 21-2. Spi Timing Diagram In Normal Mode
GD32E502xx User Manual Pin nam e Direction Description application. Slave in hardw are NSS mode: NSS input, as a chip select signal for slave. Quad-SPI configuration SPI is in single wire mode by default and enters into Quad-SPI mode after QMOD bit in SPI_QCTL register is set (only available in SPI0).
Page 553: Figure 21-3. Spi Timing Diagram In Quad-Spi Mode (Ckpl=1, Ckph=1, Lf=0)
GD32E502xx User Manual Figure 21-3. SPI timing diagram in Quad-SPI mode (CKPL=1, CKPH=1, LF=0) sample MOSI D0[4] D0[0] D1[4] D1[0] MISO D0[5] D0[1] D1[5] D1[1] D0[6] D0[2] D1[6] D1[2] D0[7] D0[3] D1[7] D1[3] In normal mode, the length of data is configured by the FF16 bit in the SPI_CTL0 register. Data length is 16 bits if FF16=1, otherwise is 8 bits.
Page 554: Table 21-4. Nss Function In Master Mode
GD32E502xx User Manual software NSS mode) goes low, the SPI automatically enters slave mode and triggers a master fault flag CONFERR. If the application wants to use NSS line to control the SPI slave, NSS should be configured to hardware output mode (SWNSSEN=0, NSSDRV=1). NSS goes low after SPI is enabled. The application may also use a general purpose IO as NSS pin to realize more flexible NSS.
Page 555 GD32E502xx User Manual Mode Description Register configuration Data pin usage BDOEN: Don’t care MSTMOD = 1 Master reception w ith RO = 1 MOSI: Not used unidirectional connection BDEN = 0 MISO: Reception BDOEN: Don’t care MSTMOD = 1 Master transmission w ith RO = 0 MOSI: Transmission bidirectional connection...
Page 556: Figure 21-4. A Typical Full-Duplex Connection
GD32E502xx User Manual Figure 21-4. A typical full-duplex connection Master Slave MISO MISO MOSI MOSI Figure 21-5. A typical simplex connection (Master: Receive, Slave: Transmit) Figure 21-6. A typical simplex connection (Master: Transmit only, Slave: Receive) Figure 21-7. A typical bidirectional connection MISO MISO MOSI...
Page 557 GD32E502xx User Manual SPI initialization sequence Before transmiting or receiving data, application should follow the SPI initialization sequence described below: If master mode or slave TI mode is used, program the PSC [2:0] bits in SPI_CTL0 register to generate SCK with desired baud rate or configure the Td time in TI mode, otherwise, ignore this step.
Page 558: Figure 21-8. Timing Diagram Of Ti Master Mode With Discontinuous Transfer
GD32E502xx User Manual receive buffer and RBNE (receive buffer not empty) will be set. The application should read SPI_DATA register to get the received data and this will clear the RBNE flag automatically. In MRU and MRB modes, hardware continuously sends clock signal to receive the next data frame, while in full-duplex master mode (MFD), hardware only receives the next data frame when the transmit buffer is not empty.
Page 559: Figure 21-9. Timing Diagram Of Ti Master Mode With Continuous Transfer
GD32E502xx User Manual Figure 21-9. Timing diagram of TI master mode with continuous transfer In master TI mode, SPI can perform continuous or non-continuous transfer. If the master writes SPI_DATA register fast enough, the transfer is continuous, otherwise non-continuous. In non-continuous transfer, there is an extra header clock cycle before each byte. While in continuous transfer, the extra header clock cycle only exists before the first byte and the following bytes’...
Page 560: Figure 21-11. Timing Diagram Of Nss Pulse With Continuous Transmit
GD32E502xx User Manual place, several additional conditions must be met, users must also set the device into master mode, and frame format should follow the normal SPI protocol, and set the data capture edge to first clock transition. In summary: NSSP = 1; MSTMOD = 1; CKPH = 0; When active, a pluse duration of least 1 SCK clock priod is inserted between successive data frames depending on internal data transmit buffer status, multiple SCK clock cycle interval is possible if the transfer buffer stays empty.
Page 561: Figure 21-12. Timing Diagram Of Quad Write Operation In Quad-Spi Mode
GD32E502xx User Manual Figure 21-12. Timing diagram of quad write operation in Quad-SPI mode Software write SPI_DATA Hardware sets TBE again sample MOSI D0[4] D0[0] D1[4] D1[0] MISO D0[5] D0[1] D1[5] D1[1] D0[6] D0[2] D1[6] D1[2] D1[7] D0[7] D0[3] D1[3] Quad read operation SPI works in quad read mode when QMOD and QRD bits are both set in SPI_QCTL register.
Page 562: Figure 21-13. Timing Diagram Of Quad Read Operation In Quad-Spi Mode
GD32E502xx User Manual Figure 21-13. Timing diagram of quad read operation in Quad-SPI mode Software writes Software writes SPI_DATA Hardware sets TBE SPI_DATA Software reads SPI_DATA sample RBNE MOSI D0[4] D0[0] D1[4] D1[0] MISO D0[5] D0[1] D1[5] D1[1] D0[6] D0[2] D1[6] D1[2] D0[7]...
Page 563 GD32E502xx User Manual Quad-SPI mode Before leaving quad wire mode or disabling SPI, software should first check that TBE bit is set and TRANS bit is cleared, then the QMOD bit in SPI_QCTL register and SPIEN bit in SPI_CTL0 register are cleared. DMA function 21.3.6.
Page 564 GD32E502xx User Manual SPI interrupts 21.3.8. Status flags  Transmit buffer empty flag (TBE) This bit is set when the transmit buffer is empty, the software can write the next data to the transmit buffer by writing the SPI_DATA register. ...
Page 565: Figure 21-14. Block Diagram Of I2S
GD32E502xx User Manual Table 21-6. SPI interrupt requests Interrupt Flag Description Clear m ethod enable bit Transmit buffer empty Write SPI_DATA register. TBEIE RBNE Receive buffer not empty Read SPI_DATA register. RBNEIE Read or w rite SPI_STAT register, CONFERR Configuration fault error then w rite SPI_CTL0 register.
Page 566: Figure 21-15. I2S Phillips Standard Timing Diagram (Dtlen=00, Chlen=0, Ckpl=0)
GD32E502xx User Manual I2S signal description 21.4.2. There are four pins on the I2S interface, including I2S_CK, I2S_WS, I2S_SD and I2S_MCK. I2S_CK is the serial clock signal, which shares the same pin with SPI_SCK. I2S_WS is the frame control signal, which shares the same pin with SPI_NSS. I2S_SD is the serial data signal, which shares the same pin with SPI_MOSI.
Page 567: Figure 21-16. I2S Phillips Standard Timing Diagram (Dtlen=00, Chlen=0, Ckpl=1)
GD32E502xx User Manual Figure 21-16. I2S Phillips standard timing diagram (DTLEN=00, CHLEN=0, CKPL=1) When the packet type is 16-bit data packed in 16-bit frame, only one write or read operation to or from the SPI_DATA register is needed to complete the transmission of a frame. Figure 21-17.
Page 568: Figure 21-21. I2S Phillips Standard Timing Diagram (Dtlen=00, Chlen=1, Ckpl=0)
GD32E502xx User Manual transmission mode, if a 24-bit data D[23:0] is going to be sent, the first data written to the SPI_DATA register should be the higher 16 bits D[23:8]. And the second one should be a 16- bit data, the higher 8 bits of this 16-bit data should be D[7:0] and the lower 8 bits can be any value.
Page 569: Figure 21-25. Msb Justified Standard Timing Diagram (Dtlen=10, Chlen=1, Ckpl=0)
GD32E502xx User Manual Figure 21-25. MSB justified standard timing diagram (DTLEN=10, CHLEN=1, CKPL=0) Figure 21-26. MSB justified standard timing diagram (DTLEN=10, CHLEN=1, CKPL=1) Figure 21-27. MSB justified standard timing diagram (DTLEN=01, CHLEN=1, CKPL=0) Figure 21-28. MSB justified standard timing diagram (DTLEN=01, CHLEN=1, CKPL=1) frame 1 (channel left) frame 2 (channel right) 24-bit data...
Page 570: Figure 21-31. Lsb Justified Standard Timing Diagram (Dtlen=01, Chlen=1, Ckpl=0)
GD32E502xx User Manual than the data length, the valid data is aligned to LSB for LSB justified standard while the valid data is aligned to MSB for MSB justified standard. The timing diagrams for the cases that the channel length is greater than the data length are shown below. Figure 21-31.
Page 571: Figure 21-35. Pcm Standard Short Frame Synchronization Mode Timing Diagram (Dtlen=00, Chlen=0, Ckpl=0)
GD32E502xx User Manual PCM standard For PCM standard, I2S_WS and I2S_SD are updated on the rising edge of I2S_CK, and the I2S_WS signal indicates frame synchronization information. Both the short frame synchronization mode and the long frame synchronization mode are available and configurable using the PCMSMOD bit in the SPI_I2SCTL register.
Page 572: Figure 21-36. Pcm Standard Short Frame Synchronization Mode Timing Diagram
GD32E502xx User Manual (DTLEN=01, CHLEN=1, CKPL=0) Figure 21-40. PCM standard short frame synchronization mode timing diagram (DTLEN=01, CHLEN=1, CKPL=1) Figure 21-41. PCM standard short frame synchronization mode timing diagram (DTLEN=00, CHLEN=1, CKPL=0) frame 1 frame 2 16-bit data 16-bit 0 Figure 21-42.
Page 573: Figure 21-45. Pcm Standard Long Frame Synchronization Mode Timing Diagram (Dtlen=10, Chlen=1, Ckpl=0)
GD32E502xx User Manual (DTLEN=00, CHLEN=0, CKPL=1) Figure 21-45. PCM standard long frame synchronization mode timing diagram (DTLEN=10, CHLEN=1, CKPL=0) Figure 21-46. PCM standard long frame synchronization mode timing diagram (DTLEN=10, CHLEN=1, CKPL=1) frame 1 frame 2 13 bits 32 bits Figure 21-47.
Page 574: Figure 21-51. Block Diagram Of I2S Clock Generator
GD32E502xx User Manual Figure 21-50. PCM standard long frame synchronization mode timing diagram (DTLEN=00, CHLEN=1, CKPL=1) I2S clock 21.4.4. Figure 21-51. Block diagram of I2S clock generator The block diagram of I2S clock generator is shown as Figure 21-51. Block diagram of I2S clock generator.
Page 575: Figure 21-52. I2S Initialization Sequence
GD32E502xx User Manual Table 21-8. Audio sampling frequency calculation formulas MCKOEN CHLEN Form ula I2SCLK / (32 * (DIV * 2 + OF)) I2SCLK / (64 * (DIV * 2 + OF)) I2SCLK / (256 * (DIV * 2 + OF)) I2SCLK / (256 * (DIV * 2 + OF)) Operation 21.4.5.
Page 576 GD32E502xx User Manual Figure 21-52. I2S initialization sequence Start Configure the DIV [7:0] bits, the OF Is the bit is 1 bit, and the MCKOEN bit to define MSTMOD the I2S bitrate and master clock Configure the CKPL bit to define the clock polarity of idle state Configure the I2SSEL bit to select I2S mode Configure the I2SSTD [1:0] bits and the PCMSMOD...
Page 577 GD32E502xx User Manual and no transmission sequence is processing in the shift register. When a half word is written to the SPI_DATA register (TBE goes low), the data is transferred from the transmit buffer to the shift register (TBE goes high) immediately. At the moment, the transmission sequence begins.
Page 578: Figure 21-53. I2S Master Reception Disabling Sequence
GD32E502xx User Manual Figure 21-53. I2S master reception disabling sequence Start If DTLEN == 2b'00&&CHLEN == 2b'1 && I2SSTD ==2b'10 ? If DTLEN == 2b'00&&CHLEN == Wait for the second last RBNE 2b'1 && I2SSTD !=2b'10 ? Wait for the last RBNE Wait for the second last RBNE Wait 17 I2S CK clock (clock on Wait one I2S clock cycle...
Page 579 GD32E502xx User Manual I2S slave reception sequence The reception sequence in slave mode is similar to that in master mode. The differences between them are described below. In slave mode, the slave has to be enabled before the external master starts the communication.
Page 580: Table 21-10. I2S Interrupt
GD32E502xx User Manual  Transmission underrun error flag (TXURERR) TXURERR will be set when the transmit buffer is empty and the valid SCK signal starts in slave transmission mode.  Reception overrun error flag (RXORERR) This situation occurs when the receive buffer is full and a newly incoming data has been completely received.
Page 581 GD32E502xx User Manual Register definition 21.5. SPI0 base address: 0x4001 3000 SPI1/I2S1 base address: 0x4000 3800 Control register 0 (SPI_CTL0) 21.5.1. Address offset: 0x00 Reset value: 0x0000 0000 This register can be accessed by half-word (16-bit) or word (32-bit). This register has no meaning in I2S mode. Reserved SWNSS BDEN...
Page 582 GD32E502xx User Manual FF16 Data frame format 0: 8-bit data frame format 1: 16-bit data frame format Receive only mode When BDEN is cleared, this bit determines the direction of transfer. 0: Full-duplex mode 1: Receive-only mode SWNSSEN NSS softw are mode enable 0: NSS hardw are mode.
Page 583 GD32E502xx User Manual Control register 1 (SPI_CTL1) 21.5.2. Address offset: 0x04 Reset value: 0x0000 0000 This register can be accessed by half-word (16-bit) or word (32-bit). Reserved Reserved TBEIE RBNEIE ERRIE TMOD NSSP NSSDRV DMATEN DMAREN Bits Fields Descriptions 31:8 Reserved Must be kept at reset value.
Page 584 GD32E502xx User Manual 1: Transmit buffer DMA is enabled. When the TBE bit in SPI_STAT is set, it w ill generate a DMA request at corresponding DMA channel. DMAREN Receive buffer DMA enable 0: Receive buffer DMA is disabled 1: Receive buffer DMA is enabled. When the RBNE bit in SPI_STA T is set, it w ill generate a DMA request at corresponding DMA channel.
Page 585 GD32E502xx User Manual 1: Configuration fault occurred. (In master mode, the NSS pin is pulled low in NSS hardw are mode or SWNSS bit is low in NSS softw are mode.) This bit is set by hardw are and cleared by a read or w rite operation on the SPI_STA T register follow ed by a w rite access to the SPI_CTL0 register.
Page 586 GD32E502xx User Manual 31:16 Reserved Must be kept at reset value. 15:0 SPI_DATA[15:0] Data transfer register The hardw are has tw o buffers, including transmit buffer and receive buffer. Write data to SPI_DATA w ill save the data to transmit buffer and read data from SPI_DA TA w ill get the data from receive buffer.
Page 587 GD32E502xx User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 RCRC[15:0] RX CRC value When the CRCEN bit of SPI_CTL0 is set, the hardw are computes the CRC value of the received bytes and saves them in RCRC register. If the data frame format is set to 8- bit data, CRC calculation is based on CRC8 standard, and saves the value in RCRC[7:0], w hen the data frame format is set to 16-bit data, CRC calculation is based on CRC16 standard, and saves the value in RCRC[15:0].
Page 588 GD32E502xx User Manual I2S control register (SPI_I2SCTL) 21.5.8. Address offset: 0x1C Reset value: 0x0000 0000 This register can be accessed by half-word (16-bit) or word (32-bit). Reserved Reserved I2SSEL I2SEN I2SOPMOD[1:0] PCMSMOD Reserved I2SSTD[1:0] CKPL DTLEN[1:0] CHLEN Bits Fields Descriptions 31:12 Reserved Must be kept at reset value.
Page 589 GD32E502xx User Manual 11: PCM standard These bits should be configured w hen I2S is disabled. These bits are not used in SPI mode. CKPL Idle state clock polarity 0: The idle state of I2S_CK is low level 1: The idle state of I2S_CK is high level This bit should be configured w hen I2S is disabled.
Page 590 GD32E502xx User Manual This bit is not used in SPI mode. Odd factor for the prescaler 0: Real divider value is DIV * 2 1: Real divider value is DIV * 2 + 1 This bit should be configured w hen I2S is disabled. This bit is not used in SPI mode.
Page 591 GD32E502xx User Manual This bit is only available in SPI0.
Page 592 GD32E502xx User Manual Comparator (CMP) Overview 22.1. The general purpose comparator CMP can work either standalone (all terminal are available on I/Os) or together with the timers. It could be used to wake up the MCU from low-power mode by an analog signal, provide a trigger source when an analog signal is in a certain condition, achieves some current control by working together with a PWM output of a timer and the DAC.
Page 593: Figure 22-1. Cmp Block Diagram
GD32E502xx User Manual Figure 22-1. CMP block diagram PSEL[2:0] BLK[2:0] MESEL[2:0] MISEL[2:0] Note: V is 1.2V. REFINT CMP inputs and outputs 22.3.1. These I/Os must be configured in analog mode in the GPIOs registers before they are selected as CMP inputs. Considering pin definitions in datasheet, the CMP output must be connected to corresponding alternate I/Os.
Page 594: Figure 22-2. The Cmp Outputs Signal Blanking
GD32E502xx User Manual 22-2. The CMP outputs signal blanking shows the comparator output blank function. Figure 22-2. The CMP outputs signal blanking Current threshold Current signal PWM signal Blanking window signal CMP outputs raw singal CMP outputs final singal CMP register write protection 22.3.3.
Page 595: Figure 22-3. Cmp Hysteresis
GD32E502xx User Manual Figure 22-3. CMP hysteresis CMP_IP CMP_IM CMP_IM-V hyst CMP_OUT CMP interrupt 22.3.6. The CMP output is connected to the EXTI and the EXTI line is exclusive to CMP. With this function, CMP can generate either interrupt or event which could be used to exit from sleep modes or deep-sleep modes.
Page 596 GD32E502xx User Manual 22.4. Register definition CMP base address：0x4001 7C00 CMP Control/status register (CMP_CS) 22.4.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved BLK[2:0] HST[1:0] OSEL[3:0] PSEL[2:0] MISEL[2:0] MESEL[2:0] PM[1:0] Reserved Bits Fields...
Page 597 GD32E502xx User Manual 000: No blanking 001: Select TIMER0_CH1 as blanking source 010: Select TIMER7_CH1 as blanking source 011: Select TIMER1_CH1 as blanking source 100~111: Reserved 17:16 HST[1:0] CMP hysteresis These bits are used to control the hysteresis level. 00: No hysteresis 01: Low hysteresis 10: Medium hysteresis 11: High hysteresis...
Page 598 GD32E502xx User Manual 100: DAC_OUT 101: Result of CMP_IM external input selection 110~111: Reserved MESEL[2:0] CMP_IM external input selection These bits are used to select the external source connected to the CMP_IM input of the CMP . 000: PC11 001: PC10 010: PB8 011: P A0 100: P A3...
Page 599 GD32E502xx User Manual Controller area network (CAN) Overview 23.1. CAN bus (Controller Area Network) is a bus standard designed to allow microcontrollers and devices to communicate with each other without a host computer. The CAN interface supports the CAN 2.0A/B protocol, ISO 11898-1:2015 and BOSCH CAN FD specification. The CAN module is a CAN Protocol controller with a very flexible mailbox system for transmitting and receiving CAN frames.
Page 600: Figure 23-1. Can Module Block Diagram
GD32E502xx User Manual FIFO.  Supports priority of message reception between mailboxes and Rx FIFO during matching process.  Rx FIFO identifier filtering, supports identifier matching against either 104 extended, 208 standard, or 416 partial (8 bit) identifiers.  Rx FIFO up to 6 frames depth, with DMA support. Function overview 23.3.
Page 601: Table 23-1. Mailbox Descriptor With 64 Byte Payload
GD32E502xx User Manual including: Tx arbitration: Find out the frame with the highest priority. Rx matching: Compare the frame data received in the Rx shift buffer (an internal mailbox descriptor) with the fields in Rx mailbox or Rx FIFO according to the configured matching order.
Page 602 GD32E502xx User Manual TIMESTAMP[15:0] Bits Fields Descriptions FD format indicator This bit is used to distinguish betw een CAN and CAN FD format frames. For reception (Rx mailbox), no need to w rite this bit, it w ill be stored w ith the value received on the CAN bus.
Page 603: Table 23-2. Data Bytes For Dlc
GD32E502xx User Manual For transmission (Tx mailbox), if this bit is set to '1' (recessive), and the bus transmits this bit as ‘0’ (dominant), then it means an arbitration loss. If this bit is set to '0' (dominant), and the bus transmits this bit as '1' (recessive), it is treated as a bit error.
Page 604: Table 23-4. Mailbox Tx Code
GD32E502xx User Manual CODE Servi RRFR CODE Meaning after Description reception FULL. It remains FULL. If a new frame is moved to the FULL mailbox after the mailbox w as serviced, the code still remains FULL. 0b0010 FULL If the mailbox is FULL and a new frame is moved to OVERRUN this mailbox before the CPU services it, the CODE field is automatically updated to OVERRUN.
Page 605 GD32E502xx User Manual CODE after CODE Meaning Description transm ission mailbox automatically becomes an Rx empty mailbox w ith the same ID. This is an intermediate code w hich is automatically w ritten to the mailbox by the controller interface w hen a matching remote request frame is received.
Page 606: Table 23-5. Mailbox Size
GD32E502xx User Manual DATA_i+2[7:0] DATA_i+3[7:0] Bits Fields Descriptions 31:24 DATA_i[7:0] Data byte i (i = 4*x - 8) Refer to DATA_i+3[7:0] descriptions. 23:16 DATA_i+1[7:0] Data byte i+1 (i = 4*x - 8) Refer to DATA_i+3[7:0] descriptions. 15:8 DATA_i+2[7:0] Data byte i+2 (i = 4*x - 8) Refer to DATA_i+3[7:0] descriptions.
Page 607: Table 23-6. Rx Fifo Descriptor
GD32E502xx User Manual of the FIFO which is the oldest message that has been received but not yet read by the CPU. The RAM region 0x90-0xDC is reserved for internal use of the FIFO. When RFEN bit in CAN_CTL0 register is 1, the RAM space which normally occupied by mailbox 6–31 with 8 byte payload is used for the ID filter table (configurable for 8 to up to 104 table elements) for receiving frames matching process into the FIFO.
Page 608 GD32E502xx User Manual 1: Frame format is extended. Remote transmission request 0: Data frames are accepted 1: Remote frames are accepted 19:16 DLC[3:0] Data length code in bytes This bit field is the length (in bytes) of the Rx payload. For reception, this bit field is w ritten by the CAN module w ith the DLC field of the received frame.
Page 609 GD32E502xx User Manual Bits Fields Descriptions 31:24 DATA_0[7:0] Data byte 0 Refer to DATA_3[7:0] descriptions. 23:16 DATA_1[7:0] Data byte 1 Refer to DATA_3[7:0] descriptions. 15:8 DATA_2[7:0] Data byte 2 Refer to DATA_3[7:0] descriptions. DATA_3[7:0] Data byte 3 Up to 8 bytes can be used for a data frame, depending on the DLC value of the mailbox.
Page 610 GD32E502xx User Manual Format A mode: ID_STD_A[10:0] Reserved RTR_A IDE_A Reserved ID_EXD_A[28:16] Reserved ID_EXD_A[15:0] Bits Fields Descriptions RTR_A Remote frame for format A This bit specifies w hether remote frames can be stored into the FIFO or not w hen matches.
Page 611 GD32E502xx User Manual 0: It indicates that remote frames are rejected and data frames can be stored. 1: It indicates that remote frames can be stored and data frames are rejected. IDE_B0 ID Extended frame 0 for format B This bit specifies w hether extended frames can be stored into the FIFO or not w hen matches.
Page 612 GD32E502xx User Manual Refer to ID_C_0[7:0] descriptions. Communication modes 23.3.3. The CAN interface has four communication modes:  Normal mode  Inactive mode  Loopback and silent mode  Monitor mode Normal mode In normal mode, the message reception and transmission, and errors are all managed normally, and all CAN protocol functions are enabled.
Page 613 GD32E502xx User Manual Loopback and silent mode To enter this mode, set the LSCMOD bit in CAN_CTL1 register to 1. In this mode, the messages are internally transmitted back to the receiver input, and the bit sent during the ACK slot in the frame acknowledge field is ignored to ensure reception transmitted by itself. Both transmit and receive interrupts are generated.
Page 614 GD32E502xx User Manual Pretended Networking mode Pretended Networking mode is used to receive wakeup messages with low power consumption. This mode can work together with MCU deepsleep mode. To enter Pretended Networking mode, set PNEN bit and PNMOD bit in CAN_CTL0 register to 1, and optionally put the MCU into deepsleep mode.
Page 615 GD32E502xx User Manual If the mailbox is active (either Tx or Rx), inactivate the mailbox by method described in Tx mailbox inactivation Rx mailbox inactivation, when Tx mailbox inactivation is performed, do the following steps, when Rx mailbox inactivation is performed, go to step 6.
Page 616: Table 23-7. Mailbox Arbitration Value(32 Bit) When Local Priority Disabled
GD32E502xx User Manual winner exists, and the CAN bus is not in SOF-DATA field / SOF-Control field of a data / remote frame or Error / Overload flag field of an Error / Overload frame.  CAN node enters Bus Integration state (refer to Bus integration state): Number of ASD[4:0] (in CAN_CTL2 register) CAN bits delay after the state.
Page 617: Table 23-8. Mailbox Arbitration Value(35 Bit) When Local Priority Enabled
GD32E502xx User Manual Table 23-8. Mailbox arbitration value(35 bit) when local priority enabled 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PRIO[2:0 ID_STD[10:0] Reserved...
Page 618 GD32E502xx User Manual register will be set. The writing of ABORT (0b1001) to the mailbox MDES0 word is blocked when shift -out of the mailbox is already finished, or when the mailbox is being trans mitted. In this situation, the abort request is captured and kept pending until the frame is transmitted successfully or failed: ...
Page 619 GD32E502xx User Manual Poll the the corresponding MSx bit in CAN_STAT register to be set, or by the interrupt when MIEx bit in CAN_INTEN register is set. Read back the CODE field to make sure that the mailbox is aborted, or transmitted. Clear the corresponding flag MSx in the CAN_STAT register.
Page 620 GD32E502xx User Manual INACTIVE). But this operation may lead to a result that a matched message lost without notice. Note: The Rx mailbox inactivation will automatically unlocks the mailbox. There is no write protection for Rx FIFO. Rx FIFO reception The Rx FIFO is 6-message deep.
Page 621 GD32E502xx User Manual if there are more than one messages in the Rx FIFO, the act of reading FDES3 word will update the Rx FIFO FDES0-FDES3 words with the next message, and CAN_RFIFOIFMN register (should be read before FDES3) will be updated at the same time, the flag MS5_RFNE remains set, and a DMA request is generated again.
Page 622 GD32E502xx User Manual matching. The matching process starts when completes the DLC field reception. Searching process  When the Rx FIFO is enabled, the RFO bit in CAN_CTL2 register gives the searching order. If RFO bit is set to 1, matching process starts from Rx mailbox to Rx FIFO. The Rx mailbox is searched from the lowest number mailbox to the higher ones.
Page 623: Table 23-9. Rx Mailbox Matching
GD32E502xx User Manual EMPTY, FULL, and OVERRUN will be searched: When IDERTR_RMF bit in CAN_CTL2 register is 0, it means the IDE field will be compared and RTR field will not be compared (regardless of bit 30 and bit 31 in related filter register).
Page 624: Table 23-10. Rx Fifo Matching
GD32E502xx User Manual filter data configurations in related filter register. Searching conditions for matched Rx FIFO Table 23-10. Rx FIFO matching: Searching conditions for matched Rx FIFO, refers to  If the FS[1:0] bits in CAN_CTL0 register is 0 or 1, it means A or B format of filter table is adopted, then all the IDE, RTR and ID fields will be compared, using bit 0 to bit 31 filter data configurations in related filter register.
Page 625 GD32E502xx User Manual The shift-in process can be cancelled for a Rx mailbox, but can not be c ancelled for the Rx FIFO. The shift-in process will be cancelled when matching one of the following situations:  The target mailbox is inactivated after the CAN bus has reached the first bit of Intermission field next to the frame that carried the message and its matching process has finished.
Page 626: Table 23-11. Interrupt Events
GD32E502xx User Manual There are four groups of registers used for matched message storage: CAN_PN_RWMxCS, CAN_PN_RWMxI, CAN_PN_RWMxD0 and CAN_PN_RWMxD1 registers, group x from 0 to 3. Therefore, four messages can be stored at most (when NMM[7:0] bits in CAN_PN_CTL0 register is larger than or equal to 4), and only the latest messages will be stored. The group x indicates the message arrival order.
Page 627 GD32E502xx User Manual  When FFT[1:0] bit field in CAN_PN_CTL0 register is configured to 1, it means a wakeup match event occurs when a frame is received with all fields (that is IDE, RTR, ID, DLC, and DATA field matched) matched. ...
Page 628 GD32E502xx User Manual DATA field matching  When DATAFT[1:0] bit field in CAN_PN_CTL0 register is configured to 0, it means the DATA field of a matched message is the same as the configured expected DATA field in CAN_PN_EDLx (x = 0,1) registers, using filter data in CAN_PN_DF0EDH0 and CAN_PN_DF1EDH1 registers.
Page 629 GD32E502xx User Manual detected) of a CAN FD frame with BRS bit set (refer to ISO11898-1 or Bosch CAN FD Specification V1.0). When BRSEN bit in CAN_FDCTL register is set to 1 (takes effect at the next message), and BRS bit in Tx mailbox is written as recessive ‘1’, then higher bit time (called as data bit time) will be used for the Data Phase of CAN FD frame, the nominal bit time will be used for the rest of the bits.
Page 630: Figure 23-2. Transmitter Delay
GD32E502xx User Manual For reception, the CRC polynomial used for CRC check is determined by the received FDF and DLC field. Note: In Classical frames, the CRC delimiter is one single recessive bit. In FD frames, the CRC delimiter may consist of one or two recessive bits. A transmitter shall send only one recessive bit as CRC delimiter, but it shall accept two recessive bits before the edge from recessive to dominant that starts the acknowledge slot.
Page 631 GD32E502xx User Manual with = TDCO[4:0] × t (23-2) offset CANCLK (23-3) offset PBS1_FD PTS_FD SYNC_SEG = (DPBS1[2:0] + 1) × t (23-4) PBS1_FD q_FD = DPTS[4:0] × t (23-5) PTS_FD q_FD = (DBAUDPSC[9:0] + 1) × t (23-6) q_FD CANCLK where the t is the measured transmitter delay, t...
Page 632 GD32E502xx User Manual (REFCNT[7:0] bits in the CAN_ERR0 register) and a Transmit Error Counter for data phase of CAN FD messages (TEFCNT[7:0] bits in the CAN_ERR0 regis ter) are used additionally only when the BRS field of the frame is set. They stop counting and keep their values when in Bus off state, and they restart counting after returned to error active state by Bus off recovery.
Page 633 GD32E502xx User Manual Bus integration state If the node starts the protocol operation during Bus off recovery, or detects the protocol exception event (the event occurs when FDEN bit in CAN_CTL0 register is set to 0, and a FDF bit of a FD frame is received), the node enters the bus integration state. In this state, the synchronicity to the CAN bus is lost.
Page 634: Figure 23-3. Can Bit Time
GD32E502xx User Manual occurs. Refers to CRCFERR and CRCERR bit in CAN_ERR1 register. Form error When a fixed-form bit field contains at least one illegal bit, a form error occurs. Refers to FMFERR and FMERR bit in CAN_ERR1 register. Stuff error Refers to STFFERR and STFERR bit in CAN_ERR1 register.
Page 635 GD32E502xx User Manual A valid edge is defined as the first toggle in a bit time from dominant to recessive bus level before the controller sends a recessive bit. If a valid edge is detected in BS1, not in SYNC_SEG, BS1 is added with up to SJW maximumly, so that the sample point is delayed.
Page 636 GD32E502xx User Manual , and N are configured by the DPTS[4:0] bits, DPBS1[2:0] bits, DPTS PBS1 PBS2 BAUDPSC DPBS2[2:0] bits, and DBAUDPSC[9:0] bits respectively in CAN_FDBT register. Timestamp A 16-bit internal counter of the CAN hardware in CAN_TIMER register is used to generate the timestamp value.
Page 637 GD32E502xx User Manual Interrupts 23.3.11. Table 23-11. Interrupt events. The CAN interrupt events and flags are list in Table 23-11. Interrupt events Flag Enable control Interrupt event Control Enable Control Register Enable bit register register Bus off BOIE CAN_CTL1 Bus off recovery BORF BORIE CAN_CTL2...
Page 638 GD32E502xx User Manual reset or system reset, so CAN will automatically enters Inactive mode for configuration of CAN registers.  Service the flags in CAN_STAT register Read the Rx mailbox or Rx FIFO descriptor contents, clear the corresponding asserted flag bit in CAN_STAT register, then read the CAN_TIMER register at last for a complete flag bit service.
Page 639 GD32E502xx User Manual  Initialize the Tx / Rx mailbox descriptors 1) If message transmission is needed, initialize the Tx mailbox descriptors. 2) If message reception is needed, initialize the Rx mailbox descriptors, if Rx FIFO is enabled, also initialize the Rx FIFO descriptors including the ID filter table elements. ...
Page 640 GD32E502xx User Manual CAN registers 23.5. CAN0 base address: 0x4001 A000 CAN1 base address: 0x4001 B000 Control register 0 (CAN_CTL0) 23.5.1. Address offset: 0x00 Reset value: 0x5900 000F All bits except bit 30, 28, 25, 19 of this register should be configured in Inactive mode only, because they are blocked by hardware in other modes.
Page 641 GD32E502xx User Manual 0: CAN is ready 1: CAN is not ready Reserved Must be kept at reset value. SWRST Softw are reset When this bit is set, CAN internal state machines and CAN registers w ill be reset. This bit is automitically cleared by hardw are w hen softw are reset is completed. 0: No effect 1: Softw are reset request INAS...
Page 642 GD32E502xx User Manual 1: Select Pretended Netw orking mode LAPRIOEN Local arbitration priority enable 0: Disable local arbitration priority 1: Enable local arbitration priority Mailbox stop transmission 0: Disable transmission abort 1: Enable transmission abort FDEN CAN FD operation enable 0: Disable CAN FD operation 1: Enable CAN FD operation Reserved...
Page 643: Bus Off
GD32E502xx User Manual Reserved BOIE ERRSIE Reserved LSCMOD TWERRIE RWERRIE Reserved BSPMOD ABORDIS TSYNC MMOD Reserved Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. BOIE Bus off interrupt enable 0: Disable Bus off interrupt 1: Enable Bus off interrupt ERRSIE Error summary interrupt enable 0: Disable error summary interrupt...
Page 644 GD32E502xx User Manual TSYNC Time synchronization enable synchronization 0: Disable time synchronization 1: Enable time Mailbox transmission order 0: Highest priority mailbox is transmitted first 1: Low est number mailbox is transmitted first MMOD Monitor mode 0: Disable Monitor mode 1: Enable Monitor mode Reserved Must be kept at reset value.
Page 645 GD32E502xx User Manual MFD15 MFD14 MFD13 MFD12 MFD11 MFD10 MFD9 MFD8 MFD7 MFD6 MFD5 MFD4 MFD3 MFD2 MFD1 MFD0 Bits Fields Descriptions 31:0 MFDx Mailbox filter data MFD31 bit is used to filter the mailbox descriptor RTR field. MFD30 bit is used to filter the mailbox descriptor IDE field. MFDx (x = 0..28) bits are used to filter the mailbox descriptor ID field.
Page 646: Bit Recessive Error
GD32E502xx User Manual rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 BRERR BDERR ACKERR CRCERR FMERR STFERR TWERRF RWERRF IDLEF ERRSI[1:0] ERRSF Reserved rc_w1 rc_w1 Bits Fields Descriptions BRFERR Bit recessive error in data phase of FD frames w ith the BRS bit set 0: No error occurrence 1: At least one bit sent as recessive is received as dominant BDFERR...
Page 647: Form Error
GD32E502xx User Manual 1: Bus off recovery sequence event occurs Synchronization flag 0: Not synchronized to the CAN bus 1: Synchronized to the CAN bus TWERRIF Tx error w arning interrupt flag This bit is not used during Bus off state. 0: No event occurrence 1: TWERRF bit in CAN_ERR1 register changes from 0 to 1 RWERRIF...
Page 648 GD32E502xx User Manual RWERRF Rx error w arning flag This bit is updated w hen exiting from Pretended Netw orking mode. 0: No event occurrence. 1: RECNT[7:0] in CAN_ERR0 register is greater than or equal to 96 IDLEF IDLE flag 0: No event occurrence 1: In Bus idle state Transmitting state...
Page 649: Msx
GD32E502xx User Manual MIE31 MIE30 MIE29 MIE28 MIE27 MIE26 MIE25 MIE24 MIE23 MIE22 MIE21 MIE20 MIE19 MIE18 MIE17 MIE16 MIE15 MIE14 MIE13 MIE12 MIE11 MIE10 MIE9 MIE8 MIE7 MIE6 MIE5 MIE4 MIE3 MIE2 MIE1 MIE0 Bits Fields Descriptions 31:0 MIEx Message transmission and reception interrupt enable When Rx FIFO is disabled, these bits are used for mailbox number x ( refers to M ailbox...
Page 650: Can_Ctl2
GD32E502xx User Manual 0: No successful transmission or reception has occurred in the mailbox descriptor 6 w hen Rx FIFO is disabled. / Rx FIFO has no w arning w hen Rx FIFO is enabled. 1: A successful transmission or reception has occurred in the mailbox descriptor 6 w hen Rx FIFO is disabled.
Page 651: Table 23-12. Rx Fifo Filter Element Number
GD32E502xx User Manual ITSRC PREEN Reserved EFDIS Reserved Bits Fields Descriptions ERRFSIE Error summary interrupt enable bit for data phase of FD frames w ith BRS bit set 0: Disable error summary interrupt for data phase of FD frames w ith BRS bit set 1: Enable error summary interrupt for data phase of FD frames w ith BRS bit set BORIE Bus off recovery interrupt enable...
Page 652 GD32E502xx User Manual 1: Mailboxes are filtered first RRFRMS Remote request frame is stored 0: Remote response frame is generated w hen a mailbox w ith CODE RANSWER is found w ith the same ID 1: Remote request frame is stored as a data frame w ithout automatic remote response frame transmitted IDERTR_RMF IDE and RTR field filter type for Rx mailbox reception...
Page 653 GD32E502xx User Manual Bits Fields Descriptions 31:21 Reserved Must be kept at reset value. 20:16 ANTM[4:0] Associated number of mailbox for transmitting the CRCTC[14:0] value This bit field contains the number of the mailbox w hich transmits the CRCTC[14 :0] value.
Page 654 GD32E502xx User Manual Reserved Reserved IDFMN[8:0] Bits Fields Descriptions 31:9 Reserved Must be kept at reset value. IDFMN[8:0] Identifier filter matching number This field is valid only w hen MS5_RFNE bit in CAN_STAT register is 1. This bit field indicates w hich ID filter table element matches the received message that is in the output of the Rx FIFO.
Page 655 GD32E502xx User Manual Phase buffer segment 1 time quantum = PBS1[4:0] + 1 PBS2[4:0] Phase buffer segment 2 Phase buffer segment 2 time quantum = PBS2[4:0] + 1 Receive FIFO/mailbox private filter x register (CAN_RFIFOMPFx)(x=0..31) 23.5.14. Address offset: 0x880 + 4  x Reset value: 0xXXXX XXXX These register is located in RAM.
Page 656 GD32E502xx User Manual Bits Fields Descriptions 31:18 Reserved Must be kept at reset value. WTOIE Wakeup timeout interrupt enable 0: Disable w akeup timeout interrupt 1: Enable w akeup timeout interrupt WMIE Wakeup match interrupt enable 0: Disable w akeup match interrupt 1: Enable w akeup match interrupt 15:8 NMM[7:0]...
Page 657 GD32E502xx User Manual 01: All fields are filtered 10: All fields except DATA field, DLC field are filtered w ith NMM[7:0] matching times 11: All fields are filtered w ith NMM[7:0] matching times Pretended Networking mode timeout register (CAN_PN_TO) 23.5.16. Address offset: 0xB04 Reset value: 0x0000 0000 All bits of this register should be configured in Inactive mode only, because they are blocked...
Page 658 GD32E502xx User Manual 1: Wakeup timeout event occured Wakeup match flag status 0: No w akeup match event occured 1: Wakeup match event occured 15:8 MMCNT[7:0] Matching message counter in Pretended Netw orking mode This bit field indicates the matching message number during Pretended Netw orking mode.
Page 659 GD32E502xx User Manual This bit field is used as expected ID field w hen IDFT[1:0] bit field in CAN_PN_ CT L0 register is 0 / 1 / 2, or is used as expected ID low threshold w hen IDFT[1:0] bit field is 3.
Page 660: Can_Pn_Ctl0
GD32E502xx User Manual Bits Fields Descriptions 31:24 DB0ELT[7:0] Data byte 0 expected low threshold in Pretended Netw orking mode Refer to DB3ELT[7:0] descriptions. 23:16 DB1ELT[7:0] Data byte 1 expected low threshold in Pretended Netw orking mode Refer to DB3ELT[7:0] descriptions. 15:8 DB2ELT[7:0] Data byte 2 expected low threshold in Pretended Netw orking mode...
Page 661 GD32E502xx User Manual Pretended Networking mode identifier filter / expected identifier 1 23.5.22. register (CAN_PN_IFEID1) Address offset: 0x B1C Reset value: 0x0000 0000 All bits of this register should be configured in Inactive mode only, because they are blocked by hardware in other modes. This register has to be accessed by word(32-bit).
Page 662 GD32E502xx User Manual This register has to be accessed by word(32-bit). DB0FD_EHT[7:0] DB1FD_EHT[7:0] DB2FD_EHT[7:0] DB3FD_EHT[7:0] Bits Fields Descriptions 31:24 DB0FD_EHT[7:0] Data byte 0 filter data / Data byte 0 expected high threshold in Pretended Netw orking mode Refer to DB3FD_EHT[7:0] descriptions. 23:16 DB1FD_EHT[7:0] Data byte 1 filter data / Data byte 1 expected high threshold in Pretended...
Page 663 GD32E502xx User Manual Bits Fields Descriptions 31:24 DB4FD_HTF[7:0] Data byte 4 filter data / Data byte 4 expected high threshold in Pretended Netw orking mode Refer to DB3FD_EHT[7:0] descriptions. 23:16 DB5FD_HTF[7:0] Data byte 5 filter data / Data byte 5 expected high threshold in Pretended Netw orking mode Refer to DB3FD_EHT[7:0] descriptions.
Page 664 GD32E502xx User Manual 19:16 RDLC[3:0] Received DLC bits The bit field indicates the valid data byte length. 15:0 Reserved Must be kept at reset value. Pretended Networking mode received wakeup mailbox x identifier 23.5.26. register (CAN_PN_RWMxI)(x=0..3) Address offset: 0xB44 + 16 * x Reset value: 0x0000 0000 This register has to be accessed by word(32-bit).
Page 665 GD32E502xx User Manual 23:16 RDB1[7:0] Received data byte 1 15:8 RDB2[7:0] Received data byte 2 RDB3[7:0] Received data byte 3 Pretended Networking mode received wakeup mailbox x data 1 register 23.5.28. (CAN_PN_RWMxD1)(x=0..3) Address offset: 0xB4C + 16 * x Reset value: 0x0000 0000 This register has to be accessed by word(32-bit).
Page 666 GD32E502xx User Manual Bits Fields Descriptions BRSEN Bit rate of data sw itch enable 0: Bit rate not sw itch 1: The bit rate shall be sw itched from the nominal bit rate to the preconfigured data bit rate during the data phase w hen BRS bit in Tx mailbox is recessive ‘1’ 30:18 Reserved Must be kept at reset value.
Page 667 GD32E502xx User Manual This register has to be accessed by word(32-bit). Reserved DBAUDPSC[9:0] Reserved DSJW[2:0] Reserved DPTS[4:0] Reserved DPBS1[2:0] Reserved DPBS2[2:0] Bits Fields Descriptions 31:30 Reserved Must be kept at reset value. 29:20 DBAUDPSC[9:0] Baud rate prescaler for data bit time The CAN data bit time baud rate prescaler.
Page 668 GD32E502xx User Manual 31:29 Reserved Must be kept at reset value. 28:24 ANTM[4:0] Associated number of mailbox for transmitting the CRCTCI[20:0] value This bit field contains the number of the mailbox w hich transmits the CRCTCI[20 :0] value for both classical and FD frames. 23:21 Reserved Must be kept at reset value.
Page 669: Table 24-1. List Of Abbreviations Used In Register
GD32E502xx User Manual Appendix 24.1. List of abbreviations used in register Table 24-1. List of abbreviations used in register abbreviations for Descriptions registers read/w rite (rw ) Softw are can read and w rite to this bit. read-only (r) Softw are can only read this bit. w rite-only (w ) Softw are can only w rite to this bit.
Page 670 GD32E502xx User Manual 24.3. Available peripherals For availability of peripherals and their number across all MCU series types, refer to the corresponding device data datasheet.
Page 671: Table 25-1. Revision History
GD32E502xx User Manual Revision history Table 25-1. Revision history Revision No. Description Date Initial Release Jul.10, 2023 1.Delete excess expression“accesses the FMC registers directly” of 2.3.7 M ass erase. 2.Add notes“ Note: The LXTAL is not supported to used as RTC clock source in 48-pin and 32-pin package”...
Page 672 Important Notice This document is the property of GigaDevice Semiconductor Inc. and its subsidiaries (the "Company"). This document, including any product of the Company described in this document (the “Product”), is owned by the Company under the intellectual property laws and treaties of the People’s Republic of China and other jurisdictions worldwide.