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GD32E502 Series
GigaDevice Semiconductor GD32E502 Series Manuals
Manuals and User Guides for GigaDevice Semiconductor GD32E502 Series. We have
1
GigaDevice Semiconductor GD32E502 Series manual available for free PDF download: User Manual
GigaDevice Semiconductor GD32E502 Series User Manual (672 pages)
Arm Cortex-M33 32-bit MCU
Brand:
GigaDevice Semiconductor
| Category:
Computer Hardware
| Size: 9 MB
Table of Contents
Table of Contents
2
List of Figures
16
List of Tables
22
System and Memory Architecture
25
Arm ® Cortex ® -M33 Processor
25
System Architecture
26
Figure 1-1. the Structure of the Cortex ® -M33 Processor
26
Table 1-1. Bus Interconnection Matrix
26
Memory Map
28
Figure 1-2. Series System Architecture of Gd32E502Xx Series
28
Table 1-2. Memory Map of Gd32E502Xx Devices
29
On-Chip SRAM Memory
32
Figure 1-3. ECC Decoder
33
On-Chip Flash Memory
34
Boot Configuration
34
Table 1-3. Boot Modes
34
System Configuration Controller
35
System Configuration Registers
36
System Configuration Register 0 (SYSCFG_CFG0)
36
System Configuration Register 1 (SYSCFG_CFG1)
37
EXTI Sources Selection Register 0 (SYSCFG_EXTISS0)
37
EXTI Sources Selection Register 1 (SYSCFG_EXTISS1)
38
EXTI Sources Selection Register 2 (SYSCFG_EXTISS2)
40
EXTI Sources Selection Register 3 (SYSCFG_EXTISS3)
41
System Configuration Register 2 (SYSCFG_CFG2)
42
System Status Register (SYSCFG_STAT)
43
System Configuration Register 3 (SYSCFG_CFG3)
44
TIMER Input Source Select Register (SYSCFG_TIMERINSEL)
45
Device Electronic Signature
47
Memory Density Information
48
Unique Device ID (96 Bits)
48
Flash Memory Controller (FMC)
50
Overview
50
Characteristics
50
Function Overview
50
Flash Memory Architecture
50
Table 2-1. Base Address and Size for 384 KB Flash Memory
51
Table 2-2. Base Address and Size for 256 KB Flash Memory
51
Table 2-3. Base Address and Size for 128KB Flash Memory
52
Table 2-4. 64KB Flash Base Address and Size for Flash Memory
53
Error Checking and Correcting (ECC)
54
Read Operations
55
Table 2-5. the Relation between WSCNT and AHB Clock Frequency When LDO Is 1.1V
55
Dual Bank Architecture with Read-While-Write (RWW) Capability
56
Unlock the Fmc_Ctlx Register
56
Page Erase
57
Mass Erase
58
Figure 2-1. Process of Page Erase Operation
58
Main Flash Programming
59
Figure 2-2. Process of Mass Erase Operation
59
Main Flash Fast Programming
61
Figure 2-3. Process of Word Program Operation
61
Figure 2-4. Process of Fa St Programming Operation
62
Check Blank Command
64
OTP Programming
64
Shared RAM
64
Data Flash Operation
65
Emulated EEPROM
66
Option Bytes 0 Erase
67
Option Bytes Programming
67
Option Bytes Description
68
Table 2-6. Option Bytes 0
69
Table 2-7. Option Bytes 1 (384K Flash or 256K Flash)
70
Table 2-8. Option Bytes 1 (128K Flash)
71
Table 2-9. Option Bytes 1 (64K Fla Sh)
72
Erase / Program Protection
73
Table 2-10. OB_BK0WP Bit for Pages Protected
74
Table 2-11. OB_BK1WP Bit for Pages Protected
74
Table 2-12. OB_DFWP Bit for Pages Protected (EFALC: Except 0X3 / 0Xc / 0Xe)
75
Table 2-13. OB_DFWP Bit for Pages Protected (EFALC: 0X3 / 0Xc / 0Xe)
75
Security Protection
76
Error Description
76
Table 2-14. OB_EPWP Bit for Protected
76
Table 2-15. PGSERR Conditions
77
Table 2-16. PGAERR Conditions
78
Table 2-17. PGERR Conditions
78
Table 2-18. WPERR Conditions
78
Register Definition
79
Wait State Register (FMC_WS)
79
ECC Control and Status Register (FMC_ECCCS)
80
Unlock Key Register 0 (FMC_KEY0)
82
Status Register 0 (FMC_STAT0)
82
Control Register 0 (FMC_CTL0)
83
Address Register 0 (FMC_ADDR0)
85
Option Byte Unlock Key Register (FMC_OBKEY)
85
Unlock Key Register 1 (FMC_KEY1)
86
Status Register 1 (FMC_STAT1)
86
Control Register 1 (FMC_CTL1)
87
Address Register 1 (FMC_ADDR1)
89
EEPROM Counter Register (FMC_EPCNT)
89
Option Byte Status Register (FMC_OBSTAT)
90
Erase / Program Protection Register 0 (FMC_WP0)
91
Erase / Program Protection Register 1 (FMC_WP1)
91
Option Byte 1 Control and Status Register (FMC_OB1CS)
91
Product ID Register (FMC_PID)
92
Power Management Unit (PMU)
94
Overview
94
Characteristics
94
Function Overview
94
Figure 3-1. Power Supply Overview
94
Backup Domain
95
VDD / VDDA Power Domain
96
Figure 3-2. Waveform of the por / PDR
96
Figure 3-3. Waveform of the BOR
97
Figure 3-5. Waveform of the OVD Threshold
97
Figure 3-4. Waveform of the LVD Threshold
98
1.1V Power Domain
99
Power Saving Modes
99
Table 3-1. Power Saving Mode Summary
101
Register Definition
102
Control Register (PMU_CTL)
102
Control and Status Register (PMU_CS)
103
Backup Registers (BKP)
106
Overview
106
Characteristics
106
Function Overview
106
RTC Clock Calibration
106
Tamper Detection
106
Register Definition
108
Backup Data Register X (Bkp_Datax) (X= 0
108
RTC Signal Output Control Register (BKP_OCTL)
108
Tamper Pin Control Register (BKP_TPCTL)
109
Tamper Control and Status Register (BKP_TPCS)
110
Reset and Clock Unit (RCU)
112
Reset Control Unit (RCTL)
112
Overview
112
Function Overview
112
Clock Control Unit (CCTL)
113
Overview
113
Figure 5-1. the System Reset Circuit
113
Figure 5-2. Clock Tree
114
Characteristics
115
Function Overview
115
Figure 5-3. HXTAL Clock Source
115
Figure 5-4. HXTAL Clock Source in Bypass Mode
116
Table 5-1. Clock Source Select
118
Table 5-2. Core Domain Voltage Selected in Deep-Sleep Mode
119
Register Definition
120
Control Register (RCU_CTL)
120
Configuration Register 0 (RCU_CFG0)
122
Interrupt Register (RCU_INT)
125
APB2 Reset Register (RCU_APB2RST)
128
APB1 Reset Register (RCU_APB1RST)
130
AHB Enable Register (RCU_AHBEN)
132
APB2 Enable Register (RCU_APB2EN)
133
APB1 Enable Register (RCU_APB1EN)
135
Backup Domain Control Register (RCU_BDCTL)
137
Reset Source /Clock Register (RCU_RSTSCK)
138
AHB Reset Register (RCU_AHBRST)
141
Configuration Register 1 (RCU_CFG1)
143
Configuration Register 2 (RCU_CFG2)
144
Voltage Key Register (RCU_VKEY)
145
Deep-Sleep Mode Voltage Register (RCU_DSV)
146
Interrupt / Event Controller (EXTI)
147
Overview
147
Characteristics
147
Interrupts Function Overview
147
Table 6-1. NVIC Exception Types in Cortex ® -M33
148
Table 6-2. Interrupt Vector Table
148
External Interrupt and Event (EXTI) Block Diagram
151
External Interrupt and Event Function Overview
151
Figure 6-1. Block Diagram of EXTI
151
Table 6-3. EXTI Source
152
Register Definition
154
Interrupt Enable Register (EXTI_INTEN)
154
Event Enable Register (EXTI_EVEN)
154
Rising Edge Trigger Enable Register (EXTI_RTEN)
155
Falling Edge Trigger Enable Register (EXTI_FTEN)
155
Software Interrupt Event Register (EXTI_SWIEV)
155
Pending Register (EXTI_PD)
156
Trigger Selection Controller (TRIGSEL)
157
Overview
157
Characteristics
157
Function Overview
157
Internal Connect
158
Figure 7-1. TRIGSEL Main Composition Example
158
Table 7-1. Trigger Input Bit Fields Selection
158
Table 7-2. TRIGSEL Input and Output Mapping
160
Register Definition
163
Trigger Selection for EXTOUT0 Register (TRIGSEL_EXTOUT0)
163
Trigger Selection for EXTOUT1 Register (TRIGSEL_EXTOUT1)
164
Trigger Selection for ADC0 Register (TRIGSEL_ADC0)
165
Trigger Selection for ADC1 Register (TRIGSEL_ADC1)
165
Trigger Selection for DAC Register (TRIGSEL_DAC)
166
Trigger Selection for TIMER0_ITI Register (TRIGSEL_TIMER0IN)
166
Trigger Selection for TIMER0_BRKIN Register (TRIGSEL_TIMER0BRKIN)
167
Trigger Selection for TIMER7_ITI Register (TRIGSEL_TIMER7IN)
168
Trigger Selection for TIMER7_BRKIN Register (TRIGSEL_TIMER7BRKIN)
169
Trigger Selection for TIMER19_ITI Register (TRIGSEL_TIMER19IN)
170
Trigger Selection for TIMER19_BRKIN Register (TRIGSEL_TIMER19BRKIN)
171
Trigger Selection for TIMER20_ITI Register (TRIGSEL_TIMER20IN)
172
Trigger Selection for TIMER20_BRKIN Register (TRIGSEL_TIMER20BRKIN)
173
Trigger Selection for TIMER1_ITI Register (TRIGSEL_TIMER1IN)
174
Trigger Selection for MFCOM Register (TRIGSEL_MFCOM)
175
Trigger Selection for CAN0 Register (TRIGSEL_CAN0)
176
Trigger Selection for CAN1 Register (TRIGSEL_CAN1)
177
General-Purpose and Alternate-Function I/Os (GPIO and AFIO)
178
Overview
178
Characteristics
178
Function Overview
178
Figure 8-1. Basic Structure of a General-Pupose I/O
179
Table 8-1. GPIO Configuration Table
179
GPIO Pin Configuration
180
External Interrupt/Event Lines
180
Alternate Functions (AF)
180
Additional Functions
180
Input Configuration
181
Output Configuration
181
Figure 8-2. Basic Structure of Input Configuration
181
Figure 8-3. Basic Structure of Output Configuration
181
Analog Configuration
182
Alternate Function (AF) Configuration
182
Figure 8-4. Basic Structure of Analog Configuration
182
Figure 8-5. Basic Structure of Alternate Function Configuration
182
GPIO Locking Function
183
GPIO Single Cycle Toggle Function
183
Register Definition
184
Port Control Register (Gpiox_Ctl, X=A
184
Port Output Mode Register (Gpiox_Omode, X=A
186
Port Output Speed Register (Gpiox_Ospd, X=A
187
Port Pull-Up/Down Register (Gpiox_Pud, X=A
189
Port Input Status Register (Gpiox_Istat, X=A
191
Port Output Control Register (Gpiox_Octl, X=A
191
Port Bit Operate Register (Gpiox_Bop, X=A
191
Port Configuration Lock Register (Gpiox_Lock, X=A
192
Alternate Function Selected Register 0 (Gpiox_Afsel0, X=A
193
Alternate Function Selected Register 1 (Gpiox_Afsel1, X=A
194
Bit Clear Register (Gpiox_Bc, X=A
195
Port Bit Toggle Register (Gpiox_Tg, X=A
196
Multi-Function Communication Interface (MFCOM)
197
Overview
197
Characteristics
197
Block Diagram
197
Figure 9-1. MFCOM Block Diagram
197
Function Overview
198
Clocking and Resets
198
Shifter
198
Figure 9-2. Shifter Microarchitecture
199
Table 9-1. Mode of Shifter
199
Timer
200
Pin
202
Interrupts and DMA Requests
203
Triggers
203
Table 9-2. MFCOM Interrupts and DMA Requests
203
Typical Configuration of Application
204
Register Definition
214
Control Register (MFCOM_CTL)
214
Pin Data Register (MFCOM_PINDATA)
214
Shifter Status Register (MFCOM_SSTAT)
215
Shifter Error Register (MFCOM_SERR)
215
Timer Status Register (MFCOM_TMSTAT)
216
Shifter Status Interrupt Enable Register (MFCOM_SSIEN)
217
Shifter Error Interrupt Enable Register (MFCOM_SEIEN)
217
Timer Status Interrupt Enable Register (MFCOM_TMSIEN)
218
Shifter Status DMA Enable Register (MFCOM_SSDMAEN)
218
Shifter Control X Register (Mfcom_Sctlx)
219
Shifter Configuration X Register (Mfcom_Scfgx)
220
Shifter Buffer X Register (Mfcom_Sbufx)
221
Shifter Buffer X Bit Swapped Register (Mfcom_Sbufbisx)
221
Shifter Buffer X Byte Swapped Register (Mfcom_Sbufbysx)
222
Shifter Buffer X Bit Byte Swapped Register (Mfcom_Sbufbbsx)
222
Timer Control X Register (Mfcom_Tmctlx)
223
Timer Configuration X Register (Mfcom_Tmcfgx)
224
Timer Compare X Register (Mfcom_Tmcmpx)
226
CRC Calculation Unit (CRC)
228
Overview
228
Characteristics
228
Figure 10-1. Block Diagram of CRC Calculation Unit
228
Function Overview
229
Register Definition
230
Data Register (CRC_DATA)
230
Free Data Register (CRC_FDATA)
230
Control Register (CRC_CTL)
231
Initialization Data Register (CRC_IDATA)
231
Polynomial Register (CRC_POLY)
232
Direct Memory Access Controller (DMA)
233
Overview
233
Characteristics
233
Block Diagram
234
Function Overview
234
DMA Operation
234
Figure 11-1. Block Diagram of DMA
234
Table 11-1. DMA Transfer Operation
235
Peripheral Handshake
236
Figure 11-2. Handshake Mechanism
236
Arbitration
237
Address Generation
237
Circular Mode
237
Memory to Memory Mode
237
Channel Configuration
237
Interrupt
238
Table 11-2. Interrupt Events
238
DMA Request Mapping
239
Figure 11-3. DMA Interrupt Logic
239
Register Definition
240
Interrupt Flag Register (DMA_INTF)
240
Interrupt Flag Clear Register (DMA_INTC)
241
Channel X Control Register (Dma_Chxctl)
241
Channel X Counter Register (Dma_Chxcnt)
243
Channel X Peripheral Base Address Register (Dma_Chxpaddr)
244
Channel X Memory Base Address Register (Dma_Chxmaddr)
244
DMA Request Multiplexer (DMAMUX)
246
Overview
246
Characteristics
246
Block Diagram
247
Function Overview
247
Figure 12-1. Block Diagram of DMAMUX
247
DMAMUX Signals
248
DMAMUX Request Multiplexer
248
Table 12-1. DMAMUX Signals
248
Figure 12-2. Synchronization Mode
249
Figure 12-3. Event Generation
250
DMAMUX Request Generator
251
Channel Configurations
252
Interrupt
252
DMAMUX Mapping
252
Table 12-2. Interrupt Events
252
Table 12-3. Request Multiplexer Input Mapping
253
Table 12-4. Trigger Input Mapping
255
Table 12-5. Synchronization Input Mapping
256
Register Definition
257
Request Multiplexer Channel X Configuration Register (Dmamux_Rm_Chxcfg)
257
Request Multiplexer Channel Interrupt Flag Register (DMAMUX_RM_INTF)
258
Request Multiplexer Channel Interrupt Flag Clear Register (DMAMUX_RM_INTC)
258
Request Generator Channel X Configuration Register (Dmamux_Rg_Chxcfg)
259
Request Generator Interrupt Flag Register (DMAMUX_RG_INTF)
260
Request Generator Interrupt Flag Clear Register (DMAMUX_RG_INTC)
260
Debug (DBG)
262
Introduction
262
JTAG/SW Function Overview
262
Switch JTAG or SW Interface
262
Pin Assignment
262
JTAG Daisy Chained Structure
263
Debug Reset
263
JEDEC-106 ID Code
263
Debug Hold Function Overview
263
Debug Support for Power Saving Mode
263
Table 13-1. Pin Assignment
263
Debug Support for TIMER, I2C, WWDGT and FWDGT
264
Registers Definition
265
ID Code Register (DBG_ID)
265
Control Register (DBG_CTL)
265
Analog-To-Digital Converter (ADC)
268
Overview
268
Characteristics
268
Pins and Internal Signals
269
Table 14-1. ADC Internal Input Signals
269
Table 14-2. ADC Input Pins Definition
269
Function Overview
270
Foreground Calibration Function
270
Figure 14-1. ADC Module Block Diagram (for ADC0 and ADC1)
270
ADC Clock
271
ADC Enable
271
Routine Sequence
271
Operation Modes
271
Figure 14-2. Single Operation Mode
271
Figure 14-3. Continuous Operation Mode
272
Figure 14-4. Scan Operation Mode, Continuous Disable
273
Figure 14-5. Scan Operation Mode, Continuous Enable
273
Conversion Result Threshold Monitor Function
274
Figure 14-6. Discontinuous Operation Mode
274
Data Alignment
275
Sample Time Configuration
275
Figure 14-7. 12-Bit Data Alignment
275
Figure 14-8. 6-Bit Data Alignment
275
External Trigger Configuration
276
DMA Request
276
ADC Internal Channels
276
Table 14-3. External Trigger Source for ADC0 and ADC1
276
Programmable Resolution (DRES)
277
Table 14-4. T CONV Timings Depending on Resolution
277
On-Chip Hardware Oversampling
278
Figure 14-9. 20-Bit to 16-Bit Result Truncation
278
ADC Sync Mode
279
Figure 14-10. Numerical Example with 5-Bits Shift and Rounding
279
Table 14-5. Maximum Output Results for N and M Combimations (Grayed Values Indicates Truncation)
279
Free Mode
280
Figure 14-11. ADC Sync Block Diagram
280
Table 14-6. ADC Sync Mode Table
280
Routine Parallel Mode
281
Routine Follow-Up Fast Mode
281
Figure 14-12. Routine Parallel Mode on 16 Channels
281
Routine Follow-Up Slow Mode
282
Figure 14-13. Routine Follow-Up Fast Mode on 1 Channel in Continuous Operation Mode .282 Figure 14-14. Routine Follow-Up Slow Mode on 1 Channel
282
ADC Interrupts
283
Register Definition
284
Status Register (ADC_STAT)
284
Control Register 0 (ADC_CTL0)
285
Control Register 1 (ADC_CTL1)
287
Sample Time Register 0 (ADC_SAMPT0)
288
Sample Time Register 1 (ADC_SAMPT1)
289
Watchdog High Threshold Register 0 (ADC_WDHT0)
290
Watchdog Low Threshold Register 0 (ADC_WDLT0)
290
Routine Sequence Register 0 (ADC_RSQ0)
291
Routine Sequence Register 1 (ADC_RSQ1)
291
Routine Sequence Register 2 (ADC_RSQ2)
292
Routine Data Register (ADC_RDATA)
293
Oversample Control Register (ADC_OVSAMPCTL)
293
Watchdog 1 Channel Selection Register (ADC_WD1SR)
295
Watchdog Threshold Register 1 (ADC_WDT1)
295
Digital-To-Analog Converter (DAC)
297
Overview
297
Characteristics
297
Figure 15-1. DAC Block Diagram
297
Function Overview
298
DAC Enable
298
DAC Output Buffer
298
DAC Data Configuration
298
DAC Trigger
298
Table 15-1. DAC I/O Description
298
DAC Workflow
299
DAC Noise Wave
299
Figure 15-2. DAC LFSR Algorithm
299
DAC Output Calculate
300
DMA Request
300
Figure 15-3. DAC Triangle Noise Wave
300
Registers Definition
301
Control Register (DAC_CTL)
301
Software Trigger Register (DAC_SWT)
302
DAC_OUT 12-Bit Right-Aligned Data Holding Register (OUT_R12DH)
303
DAC_OUT 12-Bit Left-Aligned Data Holding Register (OUT_L12DH)
303
DAC_OUT 8-Bit Right-Aligned Data Holding Register (OUT_R8DH)
304
DAC_OUT Data Output Register (OUT_DO)
304
DAC Status Register (DAC_STAT)
304
Watchdog Timer (WDGT)
306
Free Watchdog Timer (FWDGT)
306
Overview
306
Characteristics
306
Function Overview
306
Figure 16-1. Free Watchdog Block Diagram
307
Table 16-1. Min/Max FWDGT Timeout Period at 40Khz (IRC40K)
308
Register Definition
309
Window Watchdog Timer (WWDGT)
313
Overview
313
Characteristics
313
Function Overview
313
Figure 16-2. Window Watchdog Timer Block Diagram
313
Figure 16-3. Window Watchdog Timing Diagram
314
Table 16-2. Min-Max Timeout Value at 50 Mhz
315
Register Definition
316
Real-Time Clock (RTC)
318
Overview
318
Characteristics
318
Function Overview
318
RTC Reset
319
RTC Reading
319
Figure 17-1. Block Diagram of RTC
319
RTC Configuration
320
RTC Flag Assertion
320
Figure 17-3. RTC Second and Overflow Waveform Example (RTC_PSC= 3)
321
Register Definition
322
RTC Interrupt Enable Register (RTC_INTEN)
322
RTC Control Register (RTC_CTL)
322
RTC Prescaler High Register (RTC_PSCH)
323
RTC Prescaler Low Register (RTC_PSCL)
324
RTC Divider High Register (RTC_DIVH)
324
RTC Divider Low Register (RTC_DIVL)
324
RTC Counter High Register (RTC_CNTH)
325
RTC Counter Low Register (RTC_CNTL)
325
RTC Alarm High Register (RTC_ALRMH)
326
RTC Alarm Low Register (RTC_ALRML)
326
Timer
327
Table 18-1. Timers (Timerx) Are Divided into Three Sorts
327
Advanced Timer (Timerx, X=0, 7, 19, 20)
328
Overview
328
Characteristics
328
Block Diagram
329
Function Overview
329
Figure 18-1. Advanced Timer Block Diagram
329
Table 18-2. Advanced Timer Channel Description
329
Figure 18-2. Timing Chart of Internal Clock Divided by 1
330
Figure 18-3. Timing Chart of PSC Value Change from 0 to 2
331
Figure 18-4. Timing Chart of up Counting Mode, PSC=0/2
332
Figure 18-5. Timing Chart of up Counting Mode, Change Timerx_Car on the Go
333
Figure 18-6. Timing Chart of down Counting Mode, PSC=0/2
334
Figure 18-7. Timing Chart of down Counting Mode, Change Timerx_Car on the Go
334
Figure 18-8. Timing Chart of Center-Aligned Counting Mode
336
Figure 18-9. Repetition Counter Timing Chart of Center-Aligned Counting Mode
337
Figure 18-10. Repetition Counter Timing Chart of up Counting Mode
337
Figure 18-11. Repetition Counter Timing Chart of down Counting Mode
338
Figure 18-12. Channel 0 Input Capture Principle
339
Figure 18-13. Multi Mode Channel 0 Input Capture Principle
339
Figure 18-14. Channel Output Compare Principle (When Mchxmsel = 2'00, X=0, 1, 2, 3)
340
Figure 18-15. Channel Output Compare Principle (When Mchxmsel = 2'01, X=0, 1, 2, 3)
340
Figure 18-16. Channel Output Compare Principle (with Complementary Output When Mchxmsel = 2'11, X=0,1,2,3)
341
Figure 18-17. Output-Compare under Three Modes
343
Figure 18-18. EAPWM Timechart
344
Figure 18-19. CAPWM Timechart
344
Table 18-3.The Composite PWM Pulse Width
345
Figure 18-20. Channel X Output PWM with (Chxval < Chxcomval_Add)
346
Figure 18-21. Channel X Output PWM with (Chxval = Chxcomval_Add)
346
Figure 18-22. Channel X Output PWM with (Chxval > Chxcomval_Add)
346
Figure 18-23. Channel X Output PWM with Chxval or Chxcomval_Add Exceeds CARL
347
Figure 18-24. Channel X Output PWM Duty Cycle Changing with Chxcomval_Add
347
Figure 18-25. Four Channels Outputs in Composite PWM Mode
348
Figure 18-26. Chx_O Output with a Pulse in Edge -Aligned Mode (Chxompsel≠2'B00)
349
Figure 18-27. Chx_O Output with a Pulse in Center-Aligned Mode (Chxompsel≠2'B00)
349
Table 18-4. Complementary Outputs Controlled by Parameters (Mchxmsel =2'B11)
351
Figure 18-28. Channel Output Complementary PWM with Dead-Time Insertion
352
Figure 18-29. Break Function Diagram
353
Figure 18-30. Output Behavior of the Channel in Response to a Break (the Break High Active)
354
Figure 18-31. Counter Behavior with CI0FE0 Polarity Non-Inverted in Mode 2
355
Table 18-5. Counting Direction in Different Quadrature Decoder Mode
355
Figure 18-32. Counter Behavior with CI0FE0 Polarity Inverted in Mode 2
356
Figure 18-33. Hall Sensor Is Used for BLDC Motor
357
Figure 18-34. Hall Sensor Timing between Two Timers
357
Figure 18-35. Restart Mode
358
Table 18-6. Examples of Slave Mode
358
Figure 18-36. Pause Mode
359
Figure 18-37. Event Mode
359
Figure 18-38. Single Pulse Mode Timerx_Chxcv=0X04, Timerx_Car=0X99
360
Figure 18-39. TIMER0 Master/Slave Mode Example
361
Figure 18-40. Triggering TIMER0 with Enable Signal of TIMER1
362
Figure 18-41. Triggering TIMER0 and TIMER1 with Timer1'S CI0 Input
363
Registers Definition (Timerx, X=0, 7, 19, 20)
364
General Level0 Timer (Timerx, X=1)
422
Overview
422
Characteristics
422
Block Diagram
422
Figure 18-42. General Level 0 Timer Block Diagram
422
Function Overview
423
Figure 18-43. Timing Chart of Internal Clock Divided by 1
424
Figure 18-44. Timing Chart of PSC Value Change from 0 to 2
425
Figure 18-45. Timing Chart of up Counting Mode, PSC=0/2
426
Figure 18-46. Timing Chart of up Counting, Change Timerx_Car on the Go
426
Figure 18-47. Timing Chart of down Counting Mode, PSC=0/2
427
Figure 18-48. Timing Chart of down Counting Mode, Change Timerx_Car on the Go
428
Figure 18-49. Timing Chart of Center-Aligned Counting Mode
429
Figure 18-50. Channels Input Capture Principle
430
Figure 18-51. Channel Output Compare Principle (X=0,1,2,3)
431
Figure 18-52. Output-Compare under Three Modes
432
Figure 18-53. EAPWM Timechart
433
Figure 18-54. CAPWM Timechart
433
Table 18-7. Counting Direction in Different Quadrature Decoder Mode
434
Figure 18-55. Counter Behavior with CI0FE0 Polarity Non-Inverted in Mode 2
435
Figure 18-56. Counter Behavior with CI0FE0 Polarity Inverted in Mode 2
435
Table 18-8. Examples of Slave Mode
435
Figure 18-57. Restart Mode
436
Figure 18-58. Pause Mode
436
Figure 18-59. Event Mode
437
Figure 18-60. Single Pulse Mode Timerx_Chxcv = 0X04, Timerx_Car=0X99
438
Registers Definition (Timerx, X=1)
439
Basic Timer (Timerx, X=5, 6)
462
Overview
462
Characteristics
462
Block Diagram
462
Function Overview
462
Figure 18-61. Basic Timer Block Diagram
462
Figure 18-62. Timing Chart of Internal Clock Divided by 1
463
Figure 18-63. Timing Chart of PSC Value Change from 0 to 2
463
Figure 18-64. Timing Chart of up Counting Mode, PSC=0/2
464
Figure 18-65. Timing Chart of up Counting Mode, Change Timerx_Car on the Go
465
Registers Definition (Timerx, X=5, 6)
466
Universal Synchronous/Asynchronous Receiver /Transmitter (USART)
471
Overview
471
Characteristics
471
Function Overview
472
Table 19-1. Description of USART Important Pins
472
USART Frame Format
473
Figure 19-1. USART Module Block Diagram
473
Figure 19-2. USART Character Frame (8 Bits Data and 1 Stop Bit)
473
Baud Rate Generation
474
Table 19-2. Configuration of Stop Bits
474
USART Transmitter
475
Figure 19-3. USART Transmit Procedure
475
USART Receiver
476
Use DMA for Data Buffer Access
477
Figure 19-4. Oversampling Method of a Receive Frame Bit (OSB=0)
477
Figure 19-5. Configuration Step When Using DMA for USART Transmission
478
Hardware Flow Control
479
Figure 19-6. Configuration Step When Using DMA for USART Reception
479
Figure 19-7. Hardware Flow Control between Two Usarts
479
Multi-Processor Communication
480
Figure 19-8. Hardware Flow Control
480
LIN Mode
481
Synchronous Mode
482
Figure 19-9. Break Frame Occurs During Idle State
482
Figure 19-10. Break Frame Occurs During a Frame
482
Irda SIR ENDEC Mode
483
Figure 19-11. Example of USART in Synchronous Mode
483
Figure 19-12. 8-Bit Format USART Synchronous Waveform (CLEN=1)
483
Figure 19-13. Irda SIR ENDEC Module
484
Figure 19-14. Irda Data Modulation
484
Half-Duplex Communication Mode
485
Figure 19-15. ISO7816-3 Frame Format
485
Figure 19-16. USART Receive FIFO Structure
488
Table 19-3. USART Interrupt Requests
488
Figure 19-17. USART Interrupt Mapping Diagram
490
Figure 20-1. I2C Module Block Diagram
510
Table 20-1. Definition of I2C-Bus Terminology (Refer to the I2C Specification of Philips Semiconductors)
511
Figure 20-2. Data Validation
512
Figure 20-3. START and STOP Signal
513
Figure 20-4. I2C Communication Flow with 10-Bit Address (Master Transmit)
513
Figure 20-5. I2C Communication Flow with 7-Bit Address (Master Transmit)
514
Figure 20-6. I2C Communication Flow with 7-Bit Address (Master Receive)
514
Figure 20-7. I2C Communication Flow with 10-Bit Address (Master Receive When HEAD10R=0)
514
Figure 20-8. I2C Communication Flow with 10-Bit Address (Master Receive When HEAD10R=1)
514
Figure 20-9. Data Hold Time
515
Figure 20-10. Data Setup Time
516
Table 20-2. Data Setup Time and Data Hold Time
517
Figure 20-11. Data Transmission
518
Figure 20-12. Data Reception
518
Table 20-3. Communication Modes to be Shut down
518
Figure 20-13. I2C Initialization in Slave Mode
521
Figure 20-14. Programming Model for Slave Transmitting When SS=0
522
Figure 20-15. Programming Model for Slave Transmitting When SS=1
523
Figure 20-16. Programming Model for Slave Receiving
524
Figure 20-17. I2C Initialization in Master Mode
525
Figure 20-18. Programming Model for Master Transmitting (N<=255)
526
Figure 20-19. Programming Model for Master Transmitting (N>255)
527
Figure 20-20. Programming Model for Master Receiving (N<=255)
528
Figure 20-21. Programming Model for Master Receiving (N>255)
529
Table 20-4. Smbus with PEC Configuration
531
Figure 20-22. Smbus Master Transmitter and Slave Receiver Communication Flow
533
Figure 20-23. Smbus Master Receiver and Slave Transmitter Communication Flow
533
Table 20-5. I2C Error Flags
534
Table 20-6. I2C Interrupt Events
534
Figure 21-1. Block Diagram of SPI
551
Table 21-1. SPI Signal Description
551
Figure 21-2. SPI Timing Diagram in Normal Mode
552
Table 21-2. Quad-SPI Signal Description
552
Figure 21-3. SPI Timing Diagram in Quad-SPI Mode (CKPL=1, CKPH=1, LF=0)
553
Table 21-3. NSS Function in Slave Mode
553
Table 21-4. NSS Function in Master Mode
554
Table 21-5. SPI Operating Modes
554
Figure 21-4. a Typical Full-Duplex Connection
556
Figure 21-5. a Typical Simplex Connection (Master: Receive, Slave: Transmit)
556
Figure 21-6. a Typical Simplex Connection (Master: Transmit Only, Slave: Receive)
556
Figure 21-7. a Typical Bidirectional Connection
556
Figure 21-8. Timing Diagram of TI Master Mode with Discontinuous Transfer
558
Figure 21-9. Timing Diagram of TI Master Mode with Continuous Transfer
559
Figure 21-10. Timing Diagram of TI Slave Mode
559
Figure 21-11. Timing Diagram of NSS Pulse with Continuous Transmit
560
Figure 21-12. Timing Diagram of Quad Write Operation in Quad-SPI Mode
561
Figure 21-13. Timing Diagram of Quad Read Operation in Quad-SPI Mode
562
Figure 21-14. Block Diagram of I2S
565
Table 21-6. SPI Interrupt Requests
565
Figure 21-15. I2S Phillips Standard Timing Diagram (DTLEN=00, CHLEN=0, CKPL=0)
566
Figure 21-16. I2S Phillips Standard Timing Diagram (DTLEN=00, CHLEN=0, CKPL=1)
567
Figure 21-17. I2S Phillips Standard Timing Diagram (DTLEN=10, CHLEN=1, CKPL=0)
567
Figure 21-18. I2S Phillips Standard Timing Diagram (DTLEN=10, CHLEN=1, CKPL=1)
567
Figure 21-19. I2S Phillips Standard Timing Diagram (DTLEN=01, CHLEN=1, CKPL=0)
567
Figure 21-20. I2S Phillips Standard Timing Diagram (DTLEN=01, CHLEN=1, CKPL=1)
567
Figure 21-21. I2S Phillips Standard Timing Diagram (DTLEN=00, CHLEN=1, CKPL=0)
568
Figure 21-22. I2S Phillips Standard Timing Diagram (DTLEN=00, CHLEN=1, CKPL=1)
568
Figure 21-23. MSB Justified Standard Timing Diagram (DTLEN=00, CHLEN=0, CKPL=0)
568
Figure 21-24. MSB Justified Standard Timing Diagram (DTLEN=00, CHLEN=0, CKPL=1)
568
Figure 21-25. MSB Justified Standard Timing Diagram (DTLEN=10, CHLEN=1, CKPL=0)
569
Figure 21-26. MSB Justified Standard Timing Diagram (DTLEN=10, CHLEN=1, CKPL=1)
569
Figure 21-27. MSB Justified Standard Timing Diagram (DTLEN=01, CHLEN=1, CKPL=0)
569
Figure 21-28. MSB Justified Standard Timing Diagram (DTLEN=01, CHLEN=1, CKPL=1)
569
Figure 21-29. MSB Justified Standard Timing Diagram (DTLEN=00, CHLEN=1, CKPL=0)
569
Figure 21-30. MSB Justified Standard Timing Diagram (DTLEN=00, CHLEN=1, CKPL=1)
569
Figure 21-31. LSB Justified Standard Timing Diagram (DTLEN=01, CHLEN=1, CKPL=0)
570
Figure 21-32. LSB Justified Standard Timing Diagram (DTLEN=01, CHLEN=1, CKPL=1)
570
Figure 21-33. LSB Justified Standard Timing Diagram (DTLEN=00, CHLEN=1, CKPL=0)
570
Figure 21-34. LSB Justified Standard Timing Diagram (DTLEN=00, CHLEN=1, CKPL=1)
570
Figure 21-35. PCM Standard Short Frame Synchronization Mode Timing Diagram (DTLEN=00, CHLEN=0, CKPL=0)
571
Figure 21-39. PCM Standard Short Frame Synchronization Mode Timing Diagram (DTLEN=01, CHLEN=1, CKPL=0)
571
Figure 21-36. PCM Standard Short Frame Synchronization Mode Timing Diagram
572
Figure 21-37. PCM Standard Short Frame Synchronization Mode Timing Diagram
572
Figure 21-38. PCM Standard Short Frame Synchronization Mode Timing Diagram
572
Figure 21-40. PCM Standard Short Frame Synchronization Mode Timing Diagram (DTLEN=01, CHLEN=1, CKPL=1)
572
Figure 21-41. PCM Standard Short Frame Synchronization Mode Timing Diagram (DTLEN=00, CHLEN=1, CKPL=0)
572
Figure 21-42. PCM Standard Short Frame Synchronization Mode Timing Diagram (DTLEN=00, CHLEN=1, CKPL=1)
572
Figure 21-43. PCM Standard Long Frame Synchronization Mode Timing Diagram
572
Figure 21-44. PCM Standard Long Frame Synchronization Mode Timing Diagram
572
Figure 21-45. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN=10, CHLEN=1, CKPL=0)
573
Figure 21-46. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN=10, CHLEN=1, CKPL=1)
573
Figure 21-47. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN=01, CHLEN=1, CKPL=0)
573
Figure 21-48. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN=01, CHLEN=1, CKPL=1)
573
Figure 21-49. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN=00, CHLEN=1, CKPL=0)
573
Figure 21-50. PCM Standard Long Frame Synchronization Mode Timing Diagram
573
Figure 21-51. Block Diagram of I2S Clock Generator
574
Table 21-7. I2S Bitrate Calculation Formulas
574
Figure 21-52. I2S Initialization Sequence
575
Table 21-8. Audio Sampling Frequency Calculation Formulas
575
Table 21-9. Direction of I2S Interface Signals for each Operation Mode
575
Figure 21-53. I2S Master Reception Disabling Sequence
578
Table 21-10. I2S Interrupt
580
Figure 22-1. CMP Block Diagram
593
Figure 22-2. the CMP Outputs Signal Blanking
594
Figure 22-3. CMP Hysteresis
595
Figure 23-1. CAN Module Block Diagram
600
Table 23-1. Mailbox Descriptor with 64 Byte Payload
601
Table 23-2. Data Bytes for DLC
603
Table 23-3. Mailbox Rx CODE
603
Table 23-4. Mailbox Tx CODE
604
Table 23-5. Mailbox Size
606
Table 23-6. Rx FIFO Descriptor
607
Table 23-7. Mailbox Arbitration Value(32 Bit) When Local Priority Disabled
616
Table 23-8. Mailbox Arbitration Value(35 Bit) When Local Priority Enabled
617
Table 23-9. Rx Mailbox Matching
623
Table 23-10. Rx FIFO Matching
624
Table 23-11. Interrupt Events
626
Figure 23-2. Transmitter Delay
630
Figure 23-3. CAN Bit Time
634
Bus off
643
Bit Recessive Error
646
Bit Dominant Error
646
Form Error
647
Stuff Error
647
Tx Error W Arning
647
Brerr
647
Bderr
647
Twerrif
647
Rwerrif
647
Msx
649
Can_Stat
649
Ms6_Rfw
649
Ms7_Rfo
649
Can_Ctl2
650
Table 23-12. Rx FIFO Filter Element Number
651
Can_Pn_Ctl0
660
Table 24-1. List of Abbreviations Used in Register
669
Table 24-2. List of Terms
669
Table 25-1. Revision History
671
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