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DL2OO USER MANUAL Dl 200 HIGH RESOLUTION USB DAC The contents of this manual may be changed with the edition, and are subject to change without notice. Ver 1.0...
Dismantling, refitting, repairing by user in private. Causing damage by using some fittings instead of the designative or accredited ones. Cannot provide credible proof of purchase. 4.Sending it back to our company for repairing. 5.Contact your S.M.S.L Audio reseller for a return or replacement.
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DL200 Features Support MQA decoding, support MQA-CD; ESS new generation high-end digital-to-analog chip ES9039Q2M; Qualcomm latest Bluetooth chip supports LDAC 24bit/96kHz, APTX/HD, SBC, AAC; 4x high-end dual op amp OPA1612 and a large number of audio grade components; New third generation XMOS XU-316 with PCM support up to 32bit/768kHz and DSD support up to DSD512;...
DL200 Remote control Install 2 x AAA batteries as instructions. When using the remote control, point it toward the remote con-trol signal receiver on the main unit from a distance of 5 m (16 ft) or less. Do not place obstructions between the main unit and the remote control.
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DL200 Display Interface and Instructions Knob AC power input AC100-240V Remote window USB Input Indicator light Optical input MQA Indicator light Bluetooth antenna DSD Indicator light Coaxial input Display RCA output 4.4mm balanced headphone jack TRS balanced output 6.35mm headphone jack...
DL200 Instructions Knob Instructions: Short press the knob (0.5-1 second) to enter the menu, short press the knob again to enter the next level menu, enter the menu to be adjusted, rotate left and right to select, when the selection is complete, press and hold for 2 seconds to exit to the main interface.
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DL200 Function introduction PCM FILTER (Minimum phase) (Linear phase apodizing fast roll-off) (Linear phase fast roll-off) (Linear phase fast roll-off low ripple) (Linear phase slow roll-off) (Minimum phase fast roll-off) (Minimum phase slow roll-off)
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DL200 DPLL DPLL 1~9, the lower the value, the smaller the clock jitter. This DPLL setting is a unique function of ESS series products. It can adjust the bandwidth of the DPLL digital phase-locked loop circuit inside the chip, so that the chip can achieve a balance between anti-clock jitter and input tolerance.