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Renesas V850E2/MN4 Application Note
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Renesas V850E2/MN4 Application Note

Renesas V850E2/MN4 Application Note

Timer array unit control
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V850E2/MN4
Timer Array Unit Control
Introduction
This application note explains how to set up the 16-bit timer array unit A (TAUA) and 32-bit timer array unit J (TAUJ)
and also gives an outline of the operation and describes the procedure for using a sample program. The sample program
makes the TAUA generate the PWM signal and output the signal to the TAUJ and makes the TAUJ measure the width
of the signal input from the TAUA.
Target Device
V850E2/MN4 Microcontrollers
Contents
1.
Overview ........................................................................................................................................... 2
2.
Usage Environment........................................................................................................................... 3
3.
Software ............................................................................................................................................ 4
4.
Sample Application............................................................................................................................ 5
R01AN0922EJ0100 Rev.1.00
Jan 13, 2012
APPLICATION NOTE
R01AN0922EJ0100
Rev.1.00
Jan 13, 2012
Page 1 of 54

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Summary of Contents for Renesas V850E2/MN4

  • Page 1 The sample program makes the TAUA generate the PWM signal and output the signal to the TAUJ and makes the TAUJ measure the width of the signal input from the TAUA. Target Device V850E2/MN4 Microcontrollers Contents Overview ............................2 Usage Environment........................... 3 Software ............................

  • Page 2: Overview

    V850E2/MN4 Timer Array Unit Control Overview This application note illustrates the usage examples of the 16-bit TAUA (timer array unit A) and 32-bit TAUJ (timer array unit J). In the TAUA, channel 0 is set as a master channel, channel 1 is set as a slave channel, and the PWM signal is output from the TAUA1TTOUT1 pin in synchronous channel operation.

  • Page 3: Usage Environment

    • MINICUBE MINICUBE is a general-purpose in-circuit emulator from Renesas Electronics which adopts the JTAG interface system. It allows the user to debug an onboard real processor and provides highly transparent and stable emulation functionalities. An adapter is required to connect a TB board to MINICUBE.

  • Page 4: Software

    V850E2/MN4 Timer Array Unit Control Software This section describes the file organization of the sample program. File Organization The sample program consists of the files that are listed below. File Name Description Common Source File CubeSuite+ File (Tool Structure) ●...

  • Page 5: Sample Application

    V850E2/MN4 Timer Array Unit Control Sample Application This section explains how to set up the TAUA and the TAUJ. Flow Charts The flow charts of this sample program are shown below. 4.1.1 Main Processing The main processing sets up the ports and the timer array units. The timers are started, the TAUA is made to generate the PWM pulse, and then, the TAUJ is made to measure the pulse width.
  • Page 6 V850E2/MN4 Timer Array Unit Control 4.1.2 Interrupt Processing Flow The INTTUAJ0I0 interrupt function processing checks for an overflow to calculate the input PWM signal width (HIGH). Figure 4.2 Interrupt Processing Flow R01AN0922EJ0100 Rev.1.00 Page 6 of 54 Jan 13, 2012...
  • Page 7 V850E2/MN4 Timer Array Unit Control Details of TAUA Setup In this sample program, the TAUA1 is set to synchronous channel operation and PWM output function. Channel 0 in the TAUA1 is set as a master channel and set to interval timer mode. Channel 1 in the TAUA1 is set as a slave channel and set to synchronous channel output mode 1 in one count mode.
  • Page 8 TAUAnC NTm 0000H T AUAnCDRm TAUAnTTOUTm IN TTAUAnIm Figure 4.4 General Timing Diagram for PWM Output Function For specific mode setup, see “V850E2/MN4 Hardware User Manual: Renesas MCU V850E2/Mx4 microcontrollers (R01UH0011EJ).” R01AN0922EJ0100 Rev.1.00 Page 8 of 54 Jan 13, 2012...
  • Page 9 0000 0000H I NTTAUJ nIm TA UJnCSRm. TAUJnOVF Figure 4.6 General Timing Diagram for Input Signal Width Measurement Function For specific mode setup, see “V850E2/MN4 Hardware User Manual: Renesas MCU V850E2/Mx4 microcontrollers (R01UH0011EJ).” R01AN0922EJ0100 Rev.1.00 Page 9 of 54 Jan 13, 2012...
  • Page 10 V850E2/MN4 Timer Array Unit Control Register Setup This section explains how to set up the relevant registers according to the flow charts shown in section 4.1. The registers described below must be configured to control the timer I/O. 4.4.1 Port Setup In this sample program, the pin P3_1, which is used to generate the PWM signal in the TAUA, is used as TAUA1TTOUT1.
  • Page 11 V850E2/MN4 Timer Array Unit Control 4.4.2 TAUAn Prescaler Registers • TAUAn prescaler clock select register (TAUAnTPS) This register specifies the CK0, CK1, CK2, and CK3_PRE prescaler clocks for all channels. CK3 is generated by dividing CK3_PRE by the factor specified in TAUAnBRS.
  • Page 12 V850E2/MN4 Timer Array Unit Control Figure 4.8 TAUAnTPS Register Format (2/4) R01AN0922EJ0100 Rev.1.00 Page 12 of 54 Jan 13, 2012...
  • Page 13 V850E2/MN4 Timer Array Unit Control Figure 4.9 TAUAnTPS Register Format (3/4) R01AN0922EJ0100 Rev.1.00 Page 13 of 54 Jan 13, 2012...
  • Page 14 V850E2/MN4 Timer Array Unit Control Figure 4.10 TAUAnTPS Register Format (4/4) Setting example TAUA1TPS = 0x000a; /* CK0:PCLK / 2^10 */ • TAUAn prescaler baudrate value register (TAUAnBRS) This register specifies the division factor of prescaler clock CK3. CK3 is generated by dividing CK3_PRE by the factor specified in this register plus one. The PCLK prescaler for CK3_PRE is specified in TAUAnTPS.TAUAnPRS3[3:0].
  • Page 15 V850E2/MN4 Timer Array Unit Control 4.4.3 TAUAn Control Registers • TAUAn channel data register (TAUAnCDRm) This register functions either as a compare register or a capture register, depending on the operation mode specified in TAUAnCMORm.TAUAnMD[4:1]. In this sample program, the cycle of the PWM pulse is set in TAUA1CDR0 and the duty of the pulse is set in TAUA1CDR1.
  • Page 16 V850E2/MN4 Timer Array Unit Control • TAUAn channel counter register (TAUAnCNTm) This register is the channel m counter register. Figure 4.12 TAUAnCNTm Register Format (1/2) R01AN0922EJ0100 Rev.1.00 Page 16 of 54 Jan 13, 2012...
  • Page 17 V850E2/MN4 Timer Array Unit Control Figure 4.13 TAUAnCNTm Register Format (2/2) R01AN0922EJ0100 Rev.1.00 Page 17 of 54 Jan 13, 2012...
  • Page 18 V850E2/MN4 Timer Array Unit Control • TAUAn channel mode OS register (TAUAnCMORm) This register controls channel m operation. In this sample program, channel 0 in the TAUA1 is set as a master channel and set to interval timer mode. When the counter is triggered by software trigger, INTTAUA1I0 is generated at the start of operation.
  • Page 19 V850E2/MN4 Timer Array Unit Control Figure 4.15 TAUAnCMORm Register Format (2/4) R01AN0922EJ0100 Rev.1.00 Page 19 of 54 Jan 13, 2012...
  • Page 20 V850E2/MN4 Timer Array Unit Control Figure 4.16 TAUAnCMORm Register Format (3/4) R01AN0922EJ0100 Rev.1.00 Page 20 of 54 Jan 13, 2012...
  • Page 21 V850E2/MN4 Timer Array Unit Control Figure 4.17 TAUAnCMORm Register Format (4/4) R01AN0922EJ0100 Rev.1.00 Page 21 of 54 Jan 13, 2012...
  • Page 22 V850E2/MN4 Timer Array Unit Control Setting examples TAUA1CMOR0 = 0x0801; /* CK0, master, software trigger count, interval mode, int at start */ TAUA1CMOR1 = 0x0409; /* CK0, slave, INT of master as trigger, one count mode, start trigger effective */ •...
  • Page 23 V850E2/MN4 Timer Array Unit Control Figure 4.18 TAUAnTS Register Format Setting example TAUA1TS = 0x0003; /* ch 0 & ch 1 count start */ R01AN0922EJ0100 Rev.1.00 Page 23 of 54 Jan 13, 2012...
  • Page 24 V850E2/MN4 Timer Array Unit Control • TAUAn channel enable status register (TAUAnTE) This register indicates whether the counter is enabled/disabled. Figure 4.19 TAUAnTE Register Format R01AN0922EJ0100 Rev.1.00 Page 24 of 54 Jan 13, 2012...
  • Page 25 V850E2/MN4 Timer Array Unit Control • TAUAn channel stop trigger register (TAUAnTT) This register stops the counter for each channel. Figure 4.20 TAUAnTT Register Format R01AN0922EJ0100 Rev.1.00 Page 25 of 54 Jan 13, 2012...
  • Page 26 V850E2/MN4 Timer Array Unit Control 4.4.4 TAUAn Output Registers • TAUAn channel output enable register (TAUAnTOE) This register enables/disables independent channel output mode controlled by software. In this sample program, the TAUA1 is set to PWM output function. Channel 1 in the TAUA1 enables the independent macro output function.
  • Page 27 V850E2/MN4 Timer Array Unit Control • TAUAn channel output mode register (TAUAnTOM) This register specifies the output mode of each channel. In this sample program, the TAUA1 is set to PWM output function. Channel 1 in the TAUA1 is set to synchronous channel operation mode.
  • Page 28 V850E2/MN4 Timer Array Unit Control • TAUAn channel output configuration register (TAUAnTOC) This register specifies the output mode of each channel in combination with TAUAnTOMm. In this sample program, the TAUA1 is set to PWM output function. Channel 1 in the TAUA1 is set to synchronous channel operation mode 1.
  • Page 29 V850E2/MN4 Timer Array Unit Control • TAUAn channel dead time output enable register (TAUAnTDE) This register enables/disables the dead time operation for each channel. In this sample program, the TAUA disables dead time operation. Figure 4.24 TAUAnTDE Register Format Setting example TAUA1TDE = 0x0000;...
  • Page 30 V850E2/MN4 Timer Array Unit Control • TAUAn channel real-time output enable register (TAUAnTRE) This register enables/disables real-time output. This program disables real-time output. Figure 4.25 TAUAnTRE Register Format Setting example TAUA1TRE = 0x0000; /* real time output prohibit */ • TAUAn channel real-time output control register (TAUAnTRC) This register controls the real-time output trigger for each channel.
  • Page 31 V850E2/MN4 Timer Array Unit Control 4.4.5 TAUAn Channel Output Level Registers • TAUAn channel output register (TAUAnTO) This register specifies and reads the level of TAUAnTTOUTm. In this sample program, the functions of specifying and reading the level of TAUAnTTOUTm are not used.
  • Page 32 V850E2/MN4 Timer Array Unit Control 4.4.6 TAUAn Simultaneous Rewrite Registers • TAUAn channel reload data enable register (TAUAnRDE) This register enables/disables simultaneous rewrite of data registers TAUAnCDRm and TAUAnTOLm. In this sample program, the TAUA generates the PWM signal in synchronous channel operation. Simultaneous rewrite is enabled in channels 0 and 1 in the TAUA1.
  • Page 33 V850E2/MN4 Timer Array Unit Control • TAUAn channel reload data control channel select register (TAUAnRDS) This register selects the channel that controls simultaneous rewrite. In this sample program, the master channel is set as a channel that monitors the simultaneous rewrite trigger in the TAUA1.
  • Page 34 V850E2/MN4 Timer Array Unit Control • TAUAn channel reload data mode register (TAUAnRDM) This register determines when the simultaneous rewrite control signal is generated. In this sample program, the simultaneous rewrite control signal is set as the signal that is generated when the counter in the master channel starts counting.
  • Page 35 V850E2/MN4 Timer Array Unit Control 4.4.7 TAUJn Prescaler Registers • TAUJn prescaler clock select register (TAUJnTPS) This register specifies the CK0, CK1, CK2, and CK3_PRE prescaler clocks for all channels. CK3 is generated by the factor specified in TAUJnBRS. In this sample program, CK0 is specified.
  • Page 36 V850E2/MN4 Timer Array Unit Control Figure 4.31 TAUJnTPS Register Format (2/3) R01AN0922EJ0100 Rev.1.00 Page 36 of 54 Jan 13, 2012...
  • Page 37 V850E2/MN4 Timer Array Unit Control Figure 4.32 TAUJnTPS Register Format (3/3) Setting example TAUJ0TPS = 0x0000; /* CK0:PCLK / 2^0 */ • TAUJn prescaler baudrate value register (TAUJnBRS) This register specifies the division factor of prescaler clock CK3. CK3 is generated by dividing CK3_PRE by the factor specified in this register plus one. The PCLK prescaler for CK3_PRE is specified in TAUJnTPS.TAUJnPRS3[3:0].
  • Page 38 V850E2/MN4 Timer Array Unit Control 4.4.8 TAUJn Control Registers • TAUJn channel data register (TAUJnCDRm) This register functions either as a compare register or as a capture register, depending on the operation mode specified in TAUJnCMORm.TAUJnMD[4:1]. In this sample program, the TAUJ0TTIN0 signal width is estimated by a combination of the values of TAUJ0CDR0 and TAUJ0CSR0.TAUJnOVF.
  • Page 39 V850E2/MN4 Timer Array Unit Control • TAUJn channel counter register (TAUJnCNTm) This register is the channel m counter register. Figure 4.34 TAUJnCNTm Register Format R01AN0922EJ0100 Rev.1.00 Page 39 of 54 Jan 13, 2012...
  • Page 40 V850E2/MN4 Timer Array Unit Control Figure 4.35 TAUJnCNTm read values R01AN0922EJ0100 Rev.1.00 Page 40 of 54 Jan 13, 2012...
  • Page 41 V850E2/MN4 Timer Array Unit Control • TAUJn channel mode OS register (TAUJnCMORm) This register controls channel m operation. In this sample program, channel 0 in the TAUJ0 is set to capture & one count mode and disables the start trigger during operation by using the valid edge of the TAUJ0TTIN0 input signal as an external start trigger and the reverse edge as a stop trigger.
  • Page 42 V850E2/MN4 Timer Array Unit Control Figure 4.37 TAUJnCMORm Register Format (2/3) R01AN0922EJ0100 Rev.1.00 Page 42 of 54 Jan 13, 2012...
  • Page 43 V850E2/MN4 Timer Array Unit Control Figure 4.38 TAUJnCMORm Register Format (3/3) Setting example TAUJ0CMOR0 = 0x020c; /* CK0, TTIN trigger edge count, capture and one count mode, no int at start */ R01AN0922EJ0100 Rev.1.00 Page 43 of 54 Jan 13, 2012...
  • Page 44 V850E2/MN4 Timer Array Unit Control • TAUJn channel mode user register (TAUJnCMURm) This register specifies the type of valid edge detection used for the TAUJnTTINm input. In this sample program, the TAUJ is set to single operation signal width measurement and measures the width of the pulse input from TAUJ0TTIN0.
  • Page 45 V850E2/MN4 Timer Array Unit Control • TAUJn channel status register (TAUJnCSRm) This register indicates the count direction and the overflow status of channel m counter. Figure 4.40 TAUJnCSRm Register Format R01AN0922EJ0100 Rev.1.00 Page 45 of 54 Jan 13, 2012...
  • Page 46 V850E2/MN4 Timer Array Unit Control • TAUJn channel status clear register (TAUJnCSCm) This registers is a trigger register for clearing the overflow flag TAUJnCSRm.TAUJnOVF of channel m. Figure 4.41 TAUJnCSCm Register Format R01AN0922EJ0100 Rev.1.00 Page 46 of 54 Jan 13, 2012...
  • Page 47 V850E2/MN4 Timer Array Unit Control • TAUJn channel start trigger register (TAUJnTS) This register enables the counter for each channel. Figure 4.42 TAUJnTS Register Format Setting example TAUJ0TS = 0x0001; /* ch 0 count start */ R01AN0922EJ0100 Rev.1.00 Page 47 of 54...
  • Page 48 V850E2/MN4 Timer Array Unit Control • TAUJn channel enable status register (TAUJnTE) This register indicates whether the counter is enabled/disabled. Figure 4.43 TAUJnTE Register Format R01AN0922EJ0100 Rev.1.00 Page 48 of 54 Jan 13, 2012...
  • Page 49 V850E2/MN4 Timer Array Unit Control • TAUJn channel stop trigger register (TAUJnTT) This register stops the counter for each channel. Figure 4.44 TAUJnTT Register Format R01AN0922EJ0100 Rev.1.00 Page 49 of 54 Jan 13, 2012...
  • Page 50 V850E2/MN4 Timer Array Unit Control 4.4.9 TAUJn Output Registers • TAUJn channel output enable register (TAUJnTOE) This register enables or disables independent channel output mode controlled by software. In this sample program, the TAUJ is set to signal width measurement function. The TAUJ disables the independent macro output function.
  • Page 51 V850E2/MN4 Timer Array Unit Control 4.4.10 TAUJn Channel Output Level Registers • TAUJn channel output register (TAUJnTO) This register specifies and reads the level of TAUJnTTOUTm. In this sample program, the TAUJ does not use the output function. • TAUJn channel output level register (TAUJnTOL) This register specifies the output logic of the channel output bit (TAUJnTO.TAUJnTOm).
  • Page 52 V850E2/MN4 Timer Array Unit Control Function Specifications This section describes the specifications for the functions that are used by the sample program. 4.5.1 Main (main.c) [Function Name] main () [Function] Calls necessary initialization functions before entering an infinite loop. [Arguments]...
  • Page 53 V850E2/MN4 Timer Array Unit Control 4.5.4 Timer Array Unit J Control (tauj_control.c) [Function Name] tauj0_initial() [Function] Sets up the independent signal width measurement mode. [Arguments] None [Return Value] None [Startup Method] Call [SFRs Used] TAUJ0TPS, TAUJ0BRS, TAUJ0CMOR0, TAUJ0CMUR0, TAUJ0TOE, TAUJ0TOM,...
  • Page 54 V850E2/MN4 Timer Array Unit Control Website and Support Renesas Electronics Website http://www.renesas.com/ Inquiries http://www.renesas.com/inquiry All trademarks and registered trademarks are the property of their respective owners. R01AN0922EJ0100 Rev.1.00 Page 54 of 54 Jan 13, 2012...
  • Page 55 Revision Record Description Rev. Date Page Summary 1.00 Jan 13, 2012 — First edition issued...
  • Page 56 General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence.
  • Page 57 Electronics product for any application categorized as "Specific" without the prior written consent of Renesas Electronics. Further, you may not use any Renesas Electronics product for any application for which it is not intended without the prior written consent of Renesas Electronics. Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an application categorized as "Specific"...