Chipset Overview - Supermicro H8SSP-8 User Manual

H8SSP-8/H8SSP-i User's Manual
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Chipset Overview

The H8SSP-8/H8SSP-i serverboard is based on a ServerWorks' chipset composed
of two main components: the HT-2000 HyperTransport
and the HT-1000 HyperTransport
provides high performance, scalability and reliability. Its HyperTransport architecture
reduces IO bottlenecks to improve overall system performance. System memory
controllers are integrated into the processors to decrease latency.
HT-2000 SystemI/O
The HT-2000 represents Serverworks' seventh generation of SystemI/O products.
This controller hub connects to the processors over a 1GHz (Double Data Rate
results in 2GHz operation), 16x HyperTransport bus and integrates the PCI-Express,
PCI-X and Gigabit Ethernet. The HyperTransport architecture allows concurrency
between the HyperTransport bus and PCI-Express and PCI-X. The processor side
of the HT link supports transfer rates of 2000, 1600, 1000, 800 and 400 Mb/s.
HT-1000 HyperTransport I/O Hub
The HT-1000 I/O hub interconnects the CPU/host bridge with the I/O bridge via
a HyperTransport bus to provide an interface between the HT-2000 and various
subsystems including the Winbond Super I/O functions, the onboard graphics, the
IDE controller and the USB ports.
HyperTransport Technology
HyperTransport technology is a high-speed, low latency point to point link that was
designed to increase the communication speed by a factor of up to 48x between
integrated circuits. This is done partly by reducing the number of buses in the
chipset to reduce bottlenecks and by enabling a more effi cient use of memory in
multi-processor systems. The end result is a signifi cant increase in bandwidth
within the chipset.
TM TM
SystemI/O
TM Controller
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TM TM
SystemI/O
Hub. The HT-2000/1000 chipset
controller