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Clara County in the State of California, USA. The State of California, County of Santa Clara shall be the exclusive venue for the resolution of any such disputes. Supermicro's total liability for all claims will not exceed the price paid for the hardware product.
Preface Preface About This Manual This manual is written for system integrators, PC technicians and knowledgeable PC users. It provides information for the installation and use of the H8DA8/H8DAE/H8DAR-8/H8DAR-i serverboard. The H8DA8/H8DAE/H8DAR-8/ H8DAR-i is based on the AMD-8131/8111 chipset and supports single or dual AMD Opteron 200 series type processors in 940-pin microPGA ZIF sockets and up to 32 GB of DDR266 or 16 GB of DDR333/400.
Chapter 1: Introduction Chapter 1 Introduction Overview Checklist Congratulations on purchasing your computer serverboard from an acknowledged leader in the industry. Our boards are designed with the utmost attention to detail to provide you with the highest standards in quality and performance. Please check that the following items have all been included with your serverboard.
Chapter 1: Introduction Serverboard Features • Single or dual AMD Opteron 200 series 64-bit processors in 940-pin microPGA ZIF sockets Memory • Eight dual/single channel DIMM slots supporting up to 32 GB of registered ECC DDR266 or up to 16 GB of registered ECC DDR400/333 SDRAM Note: Memory capacities are halved for single CPU systems.
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H8DA8/H8DAE/H8DAR-8/H8DAR-i User’s Manual ACPI Features • Microsoft OnNow • Slow blinking LED for suspend state indicator • BIOS support for USB keyboard • Main switch override mechanism • Internal/external modem ring-on Onboard I/O • Adaptec 7902W dual channel Ultra320 SCSI controller (H8DA8 and H8DAR-8 only) •...
H8DA8/H8DAE/H8DAR-8/H8DAR-i User’s Manual Chipset Overview The H8DA8/H8DAE/H8DAR-8/H8DAR-i serverboard is based on the AMD-8131 chipset. This chipset is composed of two main components: the AMD-8131 HyperTransport PCI-X Tunnel and the AMD-8111 HyperTransport I/O Hub. The AMD-8131 chipset provides high performance and an excellent feature-set for multi-processor server solutions.
Chapter 1: Introduction PC Health Monitoring This section describes the PC health monitoring features of the H8DA8/H8DAE/ H8DAR-8/H8DAR-i. The serverboard has an onboard System Hardware Monitor chip that supports PC health monitoring. Onboard Voltage Monitors for the CPU Core voltages, Hyper Transport voltage (1.2V), memory voltage (2.5V), DDR temination voltage (1.25V), +3.3V, +5V, ±12V, +1.8V, +5V stby and +3.3V stby The onboard voltage monitor will scan these voltages continuously.
H8DA8/H8DAE/H8DAR-8/H8DAR-i User’s Manual Power Confi guration Settings This section describes the features of your serverboard that deal with power and power settings. Microsoft OnNow The OnNow design initiative is a comprehensive, system-wide approach to system and device power control. OnNow is a term for a PC that is always on but appears to be off and responds immediately to user or other requests.
Chapter 1: Introduction WOL capability. Wake-On-LAN must be enabled in BIOS. Note that Wake-On-LAN can only be used with an ATX 2.01 (or above) compliant power supply. Wake-On-Ring Header (JWOR) Wake-up events can be triggered by a device such as the external modem ringing when the system is in the SoftOff state.
H8DA8/H8DAE/H8DAR-8/H8DAR-i User’s Manual Super I/O The disk drive adapter functions of the Super I/O chip include a fl oppy disk drive controller that is compatible with industry standard 82077/765, a data separator, write pre-compensation circuitry, decode logic, data rate selection, a clock genera- tor, drive interface control logic and interrupt and DMA logic.
Chapter 2: Installation Chapter 2 Installation Static-Sensitive Devices Electrostatic Discharge (ESD) can damage electronic com ponents. To prevent dam- age to your system board, it is important to handle it very carefully. The following measures are generally suffi cient to protect your equipment from ESD. Precautions •...
H8DA8/H8DAE/H8DAR-8/H8DAR-i User's Manual Processor and Heatsink Installation Exercise extreme caution when handling and installing the proces- sor. Always connect the power cord last and always remove it be- fore adding, removing or changing any hardware components. Installing the CPU Backplates Two CPU backplates (BKT-0004) are included in the retail box.
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Chapter 2: Installation 4. With the CPU inserted into the socket, inspect the four corners of the CPU to make sure that it is properly installed and fl ush with the socket. 5. Gently press the CPU socket lever down until it locks in the plastic tab. For a dual-processor system, repeat these steps to install another CPU into the CPU#2 socket.
H8DA8/H8DAE/H8DAR-8/H8DAR-i User's Manual Mounting the Serverboard into a Chassis All serverboards and motherboards have standard mounting holes to fi t different types of chassis. Make sure that the locations of all the mounting holes for both the serverboard and the chassis match. Although a chassis may have both plastic and metal mounting fasteners, metal ones are highly recommended because they ground the serverboard to the chassis.
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Chapter 2: Installation Support The H8DA8/H8DAE/H8DAR-8/H8DAR-i supports single or dual-channel, registered ECC DDR400/333/266 SDRAM. Both interleaved and non-interleaved memory are supported, so you may populate any number of DIMM slots (see note on previous page and charts on following page). The CPU2 DIMM slots can only be accessed when two CPUs are installed (however, the CPU2 DIMM slots are not required to be populated when two CPUs are installed).
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H8DA8/H8DAE/H8DAR-8/H8DAR-i User's Manual Populating Memory Banks for 128-bit Operation CPU1 CPU1 CPU1 CPU1 CPU2 CPU2 CPU2 CPU2 DIMM1A DIMM1B DIMM2A DIMM2B DIMM1A DIMM1B DIMM2A DIMM2B Notes: X indicates a populated DIMM slot. If adding at least four DIMMs (with two CPUs installed), the confi...
Chapter 2: Installation I/O Port and Control Panel Connections The I/O ports are color coded in conformance with the PC99 specifi cation to make setting up your system easier. See Figure 2-3 below for the colors and locations of the various I/O ports. Figure 2-3.
Chapter 2: Installation HDD LED HDD LED The HDD (IDE Hard Disk Drive) LED Pin Defi nitions (JF1) connection is located on pins 13 and Pin# Defi nition 14 of JF1. Attach the IDE hard drive LED cable to display disk activity. HD Active Refer to the table on the right for pin defi...
H8DA8/H8DAE/H8DAR-8/H8DAR-i User's Manual Reset Button Reset Button Pin Defi nitions (JF1) The Reset Button connection is lo- Pin# Defi nition cated on pins 3 and 4 of JF1. Attach it to the hardware reset switch on the Reset computer case. Refer to the table on Ground the right for pin defi...
Chapter 2: Installation Serial Ports Serial Port Pin Defi nitions (COM1/COM2) Pin # Defi nition Pin # Defi nition The COM1 serial port is located be- side the VGA port. COM2 is a header on the serverboard located near the BIOS chip (see serverboard layout for location).
H8DA8/H8DAE/H8DAR-8/H8DAR-i User's Manual Extra USB Headers Extra Universal Serial Bus Headers Pin Defi nitions (USB2/3/4) Three additional USB1.1 headers USB2 USB3/4 Pin # Defi nition Pin # Defi nition (USB2/3/4) are included on the serverboard. These may be con- nected to provide front side access. A USB cable (not included) is needed Ground Ground...
Chapter 2: Installation Wake-On-LAN Wake-On-LAN Pin Defi nitions The Wake-On-LAN header is desig- (JWOL) nated JWOL. See the table on the Pin# Defi nition right for pin defi nitions. You must +5V Standby have a LAN card with a Wake-On-LAN Ground connector and cable to use the Wake- Wake-up...
H8DA8/H8DAE/H8DAR-8/H8DAR-i User's Manual Jumper Settings Explanation of Jumpers To modify the operation of the Connector serverboard, jumpers can be used to Pins choose between optional settings. Jumpers create shorts between two pins to change the function of the Jumper connector. Pin 1 is identifi ed with a square solder pad on the printed circuit board.
Chapter 2: Installation JLAN1/2 Enable/Disable JLAN1/2 Enable/Disable Jumper Settings (JPL) Change the setting of jumper JPL Jumper Setting Defi nition to enable or disable the JLAN1 and JLAN2 Gb Ethernet ports. See the Pins 1-2 Enabled table on the right for jumper settings. Pins 2-3 Disabled The default setting is enabled...
H8DA8/H8DAE/H8DAR-8/H8DAR-i User's Manual SCSI Termination Enable/ Disable (H8DA8/H8DAR-8) Jumper JPA2 and JPA3 are used to enable or disable termination for the SCSI Channel A and B connectors, re- SCSI Term. Enable/Disable Jumper Settings (JPA2/JPA3) spectively. The default setting for both Jumper Setting Defi...
Chapter 2: Installation Onboard Speaker Enable/ Disable The JD1 header allows you to use either an external speaker or the Onboard Speaker Enable/Disable internal (onboard) speaker. For an Jumper Settings (JD1) onboard speaker, close pins 6 and Pins Defi nition 7 with a jumper.
H8DA8/H8DAE/H8DAR-8/H8DAR-i User's Manual Onboard Indicators JLAN1/JLAN2 LEDs JLAN LED (Connection Speed Indicator) The Ethernet ports (located beside LED Color Defi nition the VGA port) have two LEDs. One 10 Mb/s LED indicates activity while the other Green 100 Mb/s may be green, amber or off to indicate Amber 1 Gb/s the speed of the connection.
Chapter 2: Installation Floppy, IDE and SCSI Drive Connections Use the following information to connect the fl oppy and hard disk drive cables. The fl oppy disk drive cable has seven twisted wires. A red mark on a wire typically designates the location of pin 1. A single fl...
H8DA8/H8DAE/H8DAR-8/H8DAR-i User's Manual IDE Connectors IDE Drive Connectors Pin Defi nitions (JIDE#1/JIDE#2) Pin# Defi nition Pin # Defi nition There are no jumpers to confi g- ure the onboard IDE#1 and #2 Reset IDE Ground connectors. See the table on Host Data 7 Host Data 8 the right for pin defi...
Chapter 3: Troubleshooting Chapter 3 Troubleshooting Troubleshooting Procedures Use the following procedures to troubleshoot your system. If you have followed all of the procedures below and still need assistance, refer to the ‘Technical Support Procedures’ and/or ‘Returning Merchandise for Service’ section(s) in this chapter. Always disconnect the AC power cord before adding, changing or installing any hardware components.
H8DA8/H8DAE/H8DAR-8/H8DAR-i User's Manual NOTE If you are a system integrator, VAR or OEM, a POST diagnostics card is recommended. For I/O port 80h codes, refer to App. B. Memory Errors 1. Make sure that the DIMM modules are properly and fully installed. 2.
Chapter 3: Troubleshooting 3. If you still cannot resolve the problem, include the following information when contacting us for technical support: Serverboard model and PCB revision number BIOS release date/version (this can be seen on the initial display when your system fi...
H8DA8/H8DAE/H8DAR-8/H8DAR-i User's Manual Question: Why can't I turn off the power using the momentary power on/off switch? Answer: The instant power off function is controlled in BIOS by the Power But- ton Mode setting. When the On/Off feature is enabled, the serverboard will have instant off capabilities as long as the BIOS has control of the system.
Chapter 4: BIOS Chapter 4 BIOS Introduction This chapter describes the AMIBIOS™ Setup utility for the H8DA8/H8DAE/H8DAR- 8/H8DAR-i. The AMI ROM BIOS is stored in a fl ash chip and can be easily upgraded using a fl oppy disk-based program. Note: Due to periodic changes to the BIOS, some settings may have been added or deleted and might not yet be recorded in this manual.
H8DA8/H8DAE/H8DAR-8/H8DAR-i User's Manual Main Setup When you fi rst enter AMI BIOS Setup Utility, you will see the Main setup screen. You can always return to the Main setup screen by selecting the Main tab on the top of the screen. The Main Setup screen provides you with a system overview, which includes the version, built date and ID of the AMIBIOS, the type, speed and number of the processors in the system and the amount of memory installed in the system.
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Chapter 4: BIOS IDE Confi guration Onboard PCI IDE Controller The following options are available to set the IDE controller status: Disabled will dis- able the controller. Primary will enable the primary IDE controller only. Secondary will enable the secondary IDE controller only. Both will enable both the primary and the secondary IDE controllers.
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H8DA8/H8DAE/H8DAR-8/H8DAR-i User's Manual data transfer rate of 3.3 MBs. Select 1 to allow AMI BIOS to use PIO mode 1 for a data transfer rate of 5.2 MBs. Select 2 to allow AMI BIOS to use PIO mode 2 for a data transfer rate of 8.3 MBs. Select 3 to allow AMI BIOS to use PIO mode 3 for a data transfer rate of 11.1 MBs.
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Chapter 4: BIOS Floppy Confi guration Floppy A Move the cursor to these fi elds via up and down <arrow> keys to select the fl oppy type. The options are Disabled, 360 KB 5 1/4", 1.2 MB 5 1/4", 720 KB 3½", 1.44 MB 3½”, and 2.88 MB 3½".
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H8DA8/H8DAE/H8DAR-8/H8DAR-i User's Manual Parallel Port Address This option specifi es the I/O address used by the parallel port. Select Disabled to prevent the parallel port from accessing any system resources. When the value of this option is set to Disabled, the printer port becomes unavailable. Select 378 to allow the parallel port to use 378 as its I/O port address.
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Chapter 4: BIOS BIOS --> AML ACPI Table When Enabled, BIOS-->AML exchange table pointer to be included in (X) REDT pointer list. Options are Enabled and Disabled. Headless Mode Select "Enabled" to activate the Headless Operation Mode through ACPI. The options are Enabled and Disabled.
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H8DA8/H8DAE/H8DAR-8/H8DAR-i User's Manual CPU0: CPU1 HT Link1 Width The HT link will run at the width specifi ed in this setting. Options are Auto, 2 bit, 4 bit, 8 bit and 16 bit. CPU0: PCI-X0 HT Link1 Speed The HT link will run at the speed specifi ed in this setting if it is slower than or equal to the system clock and if the board is capable.
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Chapter 4: BIOS System Health Monitor CPU Overheat Temperature Use the "+" and "-" keys to set the CPU temperature threshold to between 65 and 90 C. When this threshold is exceeded, the overheat LED on the chassis will light up and an alarm will sound. The LED and alarm will turn off once the CPU temperature has dropped to 5 degrees below the threshold set.
H8DA8/H8DAE/H8DAR-8/H8DAR-i User's Manual PCI/PnP Menu Plug & Play OS Select Yes to allow the OS to confi gure Plug & Play devices. (This is not required for system boot if your system has an OS that supports Plug & Play.) Select No to allow AMIBIOS to confi...
Chapter 4: BIOS DMA Channel 0/Channel 1/Channel 3/Channel 5/Channel 6/Channel Select Available to indicate that a specifi c DMA channel is available to be used by a PCI/PnP device. Select Reserved if the DMA channel specifi ed is reserved for a Legacy ISA device.
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H8DA8/H8DAE/H8DAR-8/H8DAR-i User's Manual Wait for ‘F1’ If Error Enable to activate the Wait for F1 if Error function. The options are Enabled and Disabled. Hit ‘DEL’ Message Display Enable to display the message telling the user to hit the DEL key to enter the setup utility.
Chapter 4: BIOS CD/DVD Drives This feature allows the user to specify the boot sequence from available CDROM drives. 1st Drive Specifi es the boot sequence for the 1st Hard Drive. Security Menu AMI BIOS provides a Supervisor and a User password. If you use both passwords, the Supervisor password must be set fi...
H8DA8/H8DAE/H8DAR-8/H8DAR-i User's Manual Chipset Menu North Bridge Confi guration Memory Confi guration Memclock Mode This setting determines how the memory clock is set. Auto has the memory clock set by the code and Limit allows the user to set a stan- dard value.
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Chapter 4: BIOS ECC Confi guration DRAM ECC Enable DRAM ECC allows hardware to report and correct memory errors au- tomatically. Options are Enabled and Disabled. MCA DRAM ECC Logging When "Enabled", MCA DRAM ECC logging and reporting is enabled. Options are Enabled and Disabled.
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H8DA8/H8DAE/H8DAR-8/H8DAR-i User's Manual South Bridge Confi guration 2.0 SMBus Controller Allows the user to Enable or Disable the SMBus controller. HT Link0 P-Comp Mode Allows user to set values for this mode. Options are Auto (hardware compensa- tion values), Data (allows user to override auto values with an absolute value), CalComp + Data (allows user to add to the generated value) and CalComp - Data (allows user to subtract from the generated value).
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Chapter 4: BIOS CalComp + Data (allows user to add to the generated value) and CalComp - Data (allows user to subtract from the generated value). HT Link0 RZ-Comp Mode Allows user to set values for this mode. Options are Auto (hardware compensa- tion values), Data (allows user to override auto values with an absolute value), CalComp + Data (allows user to add to the generated value) and CalComp - Data (allows user to subtract from the generated value).
H8DA8/H8DAE/H8DAR-8/H8DAR-i User's Manual Power Menu Power Button Mode Allows the user to change the function of the power button. Options are Instant Off and 4-Sec. Delay. Restore on AC Power Loss This setting allows you to choose how the system will react when power returns after an unexpected loss of power.
Chapter 4: BIOS Exit Menu Select the Exit tab from AMI BIOS Setup Utility screen to enter the Exit BIOS Setup screen. Save Changes and Exit When you have completed the system confi guration changes, select this option to leave BIOS Setup and reboot the computer, so the new system confi guration parameters can take effect.
Appendix A: BIOS Error Beep Codes Appendix A BIOS Error Beep Codes During the POST (Power-On Self-Test) routines, which are performed each time the system is powered on, errors may occur. Non-fatal errors are those which, in most cases, allow the system to continue the boot-up process.
Appendix B: BIOS POST Checkpoint Codes Appendix B BIOS POST Checkpoint Codes When AMIBIOS performs the Power On Self Test, it writes checkpoint codes to I/O port 0080h. If the computer cannot complete the boot process, diagnostic equipment can be attached to the computer to read I/O port 0080h. Uncompressed Initialization Codes The uncompressed initialization checkpoint codes are listed in order of execution: Checkpoint...
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H8DA8/H8DAE/H8DAR-8/H8DAR-i User's Manual Bootblock Recovery Codes The bootblock recovery checkpoint codes are listed in order of execution: Checkpoint Code Description The onboard fl oppy controller if available is initialized. Next, beginning the base 512 KB memory test. Initializing the interrupt vector table next. Initializing the DMA and Interrupt controllers next.
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Appendix B: BIOS POST Checkpoint Codes Uncompressed Initialization Codes The following runtime checkpoint codes are listed in order of execution. These codes are uncompressed in F0000h shadow RAM. Checkpoint Code Description The NMI is disabled. Next, checking for a soft reset or a power on condition. The BIOS stack has been built.
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H8DA8/H8DAE/H8DAR-8/H8DAR-i User's Manual Checkpoint Code Description Interrupt vector initialization is done. Clearing the password if the POST DIAG switch is on. Any initialization before setting video mode will be done next. Initialization before setting the video mode is complete. Confi guring the mono- chrome mode and color mode settings next.
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Appendix B: BIOS POST Checkpoint Codes Checkpoint Code Description The memory below 1 MB has been cleared via a soft reset. Clearing the memory above 1 MB next. The memory above 1 MB has been cleared via a soft reset. Saving the memory size next.
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H8DA8/H8DAE/H8DAR-8/H8DAR-i User's Manual Checkpoint Code Description The password was checked. Performing any required programming before WIN- BIOS Setup next. The programming before WINBIOS Setup has completed. Uncompressing the WINBIOS Setup code and executing the AMIBIOS Setup or WINBIOS Setup utility next.
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Appendix B: BIOS POST Checkpoint Codes Checkpoint Code Description Returned from adaptor ROM at E000h control. Performing any initialization required after the E000 option ROM had control next. Initialization after E000 option ROM control has completed. Displaying the system confi guration next. Uncompressing the DMI data and executing DMI POST initialization next.
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H8DA8/H8DAE/H8DAR-8/H8DAR-i User's Manual (continued from front) The products sold by Supermicro are not intended for and will not be used in life support systems, medical equipment, nuclear facilities or systems, aircraft, aircraft devices, aircraft/emergency com- munication devices or other critical systems whose failure to perform be reasonably expected to result in signifi...
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