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3.5 C
F
HIPSET
When you select the "CHIPSET FEATURES SETUP" on the main program, the screen
display will appears as:
Chipset Features Setup Screen
CMOS Setup Utility – Copyright © 1984-2001 Award Software
Bank 0/1 DRAM Timing
Bank 2/3 DRAM Timing
Bank 4/5 DRAM Timing
DRAM Clock
SDRAM Cycle Length
Memory Hole
P2C/C2P Concurrency
System BIOS Cacheable
AGP Aperture Size
AGP Driving Control
X
AGP Driving Value
AGP Fast Write
Power-Supply Type
OnChip USB
X
USB Keyboard Support
CPU to PCI Write Buffer
PCI Dynamic Bursting
PCI Master 0 WS Write
PCI Delay Transaction
PCI#2 Access #1 Retry
AGP Master 1 WS Writer
AGP Master 1 WS Read
Memory Parity / ECC Check
Move
Enter: Select
F5: Previous Values F6: Fail-Safe Defaults
Bank 0/1 DRAM Timing / Bank 2/3 DRAM Timing /Bank 4/5 DRAM Timing: The DRAM
timing is controlled by the DRAM Timing Registers. The Timings programmed into this
register are dependent on the system design. Slower rates may be required in certain
system designs to support loose layouts or slower memory.
S
EATURES
ETUP
Advanced Chipset Features
Fast
Fast
Fast
Host CLK
3
Disabled
Enabled
Disabled
64M
Auto
DA
Disabled
AT
Disabled
Disabled
Enabled
Enabled
Enabled
Enabled
Enabled
Disabled
Disabled
Enabled
+/-/PU/PD: Value
▲
▼
F10: Save Esc: Exit F1: General Help
F7: Optimized Defaults
~ 29 ~
AWARD BIOS SETUP
Item Help
Menu Level ►
Enabled adds a parity
check to the boot-up
memory tests.
Select
Enabled
only
if
the
system DRAM contains
parity.
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