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Cypress CY82C599 Manual

Intelligent pci bus controller
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Features
D
Provides an interface between the PCI
Local Bus and the CPU bus
D
PCI Bus Rev. 2.0 compliant
R
D
Supports Intel
486DX, 486DX2,
486SX, 486SL, P24T, AMD AM486
and Cyrix Cx486S2 (M6/M7) CPUs
D
Interfaces with Cypress CY82C596 or
CY82C297 Core Logic devices to form
a complete PC solution supporting
PCI, VESA, and ISA buses
System Block Diagram
CONTROL
A[31:2]
D[31:0]
DATA
SRAM
(64K-1M)
A[19:4]
CPU
Intel
AMD
Cyrix
Cypress Semiconductor Corporation
D
Supports 4 PCI Masters
D
Supports burst mode PCI accesses to
memory space
D
PCI pre read support with
4 double word deep FIFO, each
double word is 32 Data bits wide
D
PCI post write support with
4 double word deep FIFO, each
double word is 32 Data bits wide
PCI LOCAL BUS
CY82C599
A[19:4]
CQ[15:8]
TAG
SRAM
CY82C596
or
CY82C597
MA[11:0]
DRAM
(1MB - 128MB)
VESA LOCAL BUS
3901 North First Street
D
PRELIMINARY
Intelligent PCI Bus Controller
D
Synchronous/Asynchronous PCI bus
support
D
Standby mode slows down CPU clock
D
Power management timers
D
SMI generation support for Intel,
AMD, Cyrix CPUs
D
Provides I/O trap for peripheral
device power control
D
Packaged in 160 pin PQFP
OPTIONAL
BUFFER CHIP
BUFFER
CQ[15:0]
BUFFER
ALS245
BUFFER
CQ[15:0]
CQ[7:0]
BIOS
ROM
CQ[7:0]
KYB
8042
CQ[7:0]
CY82C206
San Jose
D
D
1
June 1994 - Revised September 1994
CY82C599
LA[23:17]
SA[19:0]
LS245
SD[15:0]
CONTROL
LS245
82C599 1
CA 95134
408-943-2600
D

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Summary of Contents for Cypress CY82C599

  • Page 1 Cyrix Cx486S2 (M6/M7) CPUs Provides I/O trap for peripheral 4 double word deep FIFO, each device power control Interfaces with Cypress CY82C596 or double word is 32 Data bits wide CY82C297 Core Logic devices to form Packaged in 160 pin PQFP...
  • Page 2 PRELIMINARY CY82C599 Pin Configurations PQFP Top View 160 159 154 153 152 151 150 149 148 147 138 137 136 133 132 129 128 127 124 123 AD31 REQ0 CBE0 REQ1 REQ2 GNT0 GNT1 GNT2 GNT3 REQ3 PCICLK INTLI/A30 INTEO/A29...
  • Page 3 During this cycle, control of the Address/Data The CY82C599 has built in interrupt logic that can convert a lines is transferred from the master to the slave, who must now level sensitive interrupt signal to an edge triggered interrupt use these lines to drive out the requested information.
  • Page 4 4.2 Memory Address Space Target and the Arbiter, recognize that the current transaction is The CY82C599 supports up to 256MB of local memory space coming to an end. This advanced notice allows the Arbiter to (128MB when used with the CY82C596/7). The full 4GB grant ownership of the bus to the next requesting agent.
  • Page 5 The PCI arbitration algorithm is user selectable When a CPU bus cycle is claimed by the CY82C599, the CC state through register 30h, and can be either fixed or rotating priority. machine is in control of the CY82C599 Interface.
  • Page 6 DEVSEL and behave as the PCI target. are considered to have the same priority. The CY82C599 will The CY82C599 will also start a CPU bus as soon as possible and claim I/O transactions to PCI address space by asserting LDEV . initiate an ISA/VESA cycle.
  • Page 7 CY82C599 (contact the factory for details). In the Full speed state, the CY82C599 will monitor all stand by 9.0 Power Management Mode events. If no events occur within the period specified by the stand by timer, the CY82C599 will enter the Stand by state and The CY82C599 implements flexible power management logic.
  • Page 8 10.0 Control Registers memory block, the block sizes, and the mapping selection for This section summarizes the registers in the CY82C599. each block : Local DRAM region, PCI region or ISA region. It is The on chip registers are accessed via I/O sequence 22H and best to specify all Non Local DRAM memory areas below 23H.
  • Page 9 PRELIMINARY CY82C599 Index 24H Function Hardware Recommended Default BIOS power on setting Memory Block 0 Base Address: A15 : A14 User selectable Memory Block 0 Function Select User selectable Disable (Default) Local DRAM Region PCI Region ISA /VESA Region Memory Block 0 Size Select:...
  • Page 10 PRELIMINARY CY82C599 Index 27H Function Hardware Recommended Default BIOS power on setting Memory Block 1 Base Address: A15 : A14 User selectable Memory Block 1 Function Select User selectable Disable (Default) Local DRAM Region PCI Region ISA/VESA Region Memory Block 1 Size Select:...
  • Page 11 Enable Parallel Port Detection Enable User selectable Disable Enable Hard Disk Detection Enable User selectable Disable Enable CY82C599 Hold Detection Enable User selectable Disable Enable Non Motherboard Memory Detection Enable User selectable Disable Enable Non Motherboard I/O Detection Enable User selectable...
  • Page 12 PRELIMINARY CY82C599 Index 2DH Function Hardware Recommended Default BIOS power on setting Reserved Green Feature Timer Select (see Register 2DH, Bits 3:0). User selectable PCI Master Detection Enable User selectable Disable Enable Floppy Disk Detection Enable User selectable Disable Enable...
  • Page 13 PRELIMINARY CY82C599 Index 30H Function Hardware Recommended Default BIOS power on setting PCI Function Enable Disable Enable Reserved LRDY Delay Enable Disable Enable Reserved Arbitration Fast Interface Enable Disable Enable PCI Hidden Arbitration Mode Enable Disable Enable Reserved PCI Arbitration Rotate Priority Enable...
  • Page 14 PRELIMINARY CY82C599 Index 33H Function Hardware Recommended Default BIOS power on setting CPU Master CPU State Machine I/O Post Write Cycle Enable Disable Enable Reserved CPU Master PCI Retry Disable (Default) Infinite CPU Master Write Burst Mode Enable Disable Enable...
  • Page 15 PRELIMINARY CY82C599 Index 34H Function Hardware Recommended Default BIOS power on setting Reserved PCI Master Post Write Buffer Enable Disable Enable Note: Register 34 Bit 6 and Register 35, Bit4 together control the Post write funcitonality. See below for desired register settings.
  • Page 16 PRELIMINARY CY82C599 Index 35H Function Hardware Recommended Default BIOS power on setting PCI Master PCI State Machine Data Write 0WS Enable Disable Enable PCI Master PCI State Machine Burst Mode Enable Disable Enable PCI Master State Machine Fast Interface Enable...
  • Page 17 PRELIMINARY CY82C599 Index 37H Function Hardware Recommended Default BIOS power on setting Reserved 00000 11111 Configuration Register TARGET ABORT Status Bit Enable Disable Enable PERR External Support Enable Disable Enable SERR External Support Enable Disable Enable Index 38H Function Hardware...
  • Page 18 PRELIMINARY CY82C599 Index 3AH Function Hardware Recommended Default BIOS power on setting Shadow Block C0000h : C3FFFh 0000 User selectable Bits Bits Function Function Disable Disable Local DRAM Read Local DRAM Write PCI Read PCI Write ISA/VESA Read ISA/VESA Write...
  • Page 19 PRELIMINARY CY82C599 Index 3DH Function Hardware Recommended Default BIOS power on setting Shadow Block D8000h : DBFFFh 0000 User selectable Bits Bits Function Function Disable Disable Local DRAM Read Local DRAM Write PCI Read PCI Write ISA/VESA Read ISA/VESA Write...
  • Page 20 PRELIMINARY CY82C599 Index 40H Function Hardware Recommended Default BIOS power on setting Reserved. Must be set to 1 after power on. Reserved. Reserved, Must be set to 1 after power on. I/O write 22H, 23H, & 61H LDEV mask enable.
  • Page 21 PRELIMINARY CY82C599 Index 46H Function Hardware Recommended Default BIOS power on setting PCI Memory Block 2 Enable (A31=1, A27=0, A26=1 Disable Enable PCI Memory Block 2 Address Select A30, A29, A28 PCI Memory Block 3 Enable (A31=1, A27=1, A26=0 Disable...
  • Page 22 PRELIMINARY CY82C599 Index 49H Function Hardware Recommended Default BIOS power on setting ISA/VESA I/O space 0180H to 018FH select enable. User selectable ISA/VESA I/O space 0190H to 019FH select enable. User selectable ISA/VESA I/O space 01A0H to 01AFH select enable.
  • Page 23 PRELIMINARY CY82C599 Index 4CH Function Hardware Recommended Default BIOS power on setting ISA/VESA I/O space 0300H to 030FH select enable. User selectable ISA/VESA I/O space 0310H to 031FH select enable. User selectable ISA/VESA I/O space 0320H to 032FH select enable.
  • Page 24 PRELIMINARY CY82C599 Index 4FH Function Hardware Recommended Default BIOS power on setting PCI I/O space 01F0H to 01FFH select enable. User selectable PCI I/O space 03F6H to 03F7H select enable. User selectable PCI I/O space 0170H to 017FH select enable.
  • Page 25 PRELIMINARY CY82C599 The suspend timer is enabled when register 52 bit 1=0. When When the INTR input becomes active, the 82C599 will deassert enabled, the suspend timer always follows the stand by timer (i.e., STOPCLK and start the interrupt timer.
  • Page 26 After the new terminal count has been reached, the 82C599 will initiate another SMI. Disable Software Reset Mask Normal Force CY82C599 to inactivate pin 112. This bit should be set to "1", then set to "0" before leaving SMI subroutine.
  • Page 27 0000 0000 Bits User selectable Normal Enable power down LED to flush when 82C599 is in power down mode. CY82C599 uses pin 60 to control LED. Bits User selectable LED is active HIGH LED is active LOW . Bits User selectable INTEL SMM mode CYRIX/AMD SMM mode.
  • Page 28 Enable Quick Power Down mode. Reserved. The 82C599 supports Quick Power Down through pin 18. When pin 18 is selected, the CY82C599 will bring itself into Power Down Mode in 3 seconds if no event is detected, and Register 57, Bit 4=1.
  • Page 29 SMI caused by timer 4 reset by an event SMI pin is active The CY82C599 has two status registers (16 bits total) that can be Register 58 contains the source of an SMI and some internal read through register 58. Writing a 0 into bit 7 will cause A status status.
  • Page 30 PRELIMINARY CY82C599 Register 5A: Timer 3 Event Detection Control Function Hardware Recommended Default BIOS power on setting Bits User selectable Disable key board event detection Enable key board event detection Bits User selectable Disable serial port event detection Enable serial port event detection...
  • Page 31 PRELIMINARY CY82C599 Index 5B: Timer 3 Control Function Hardware Recommended Default BIOS power on setting Bits Terminal Time User selectable 0000: 1 sec. 0001: 1.8 sec 0010: 3.5 sec 0011: 7 sec. 0100: 14 sec. 0101: 28 sec. 0110: 56 sec.
  • Page 32 PRELIMINARY CY82C599 Index 5C: Timer 4 Event Detection Control Function Hardware Recommended Default BIOS power on setting Bits User selectable Disable key board event detection Enable key board event detection Bits User selectable Disable serial port event detection Enable serial port event detection...
  • Page 33 PRELIMINARY CY82C599 Index 5D: Timer 4 Control Function Hardware Recommended Default BIOS power on setting Bits Terminal Time User selectable 0000: 1 sec. 0001: 1.8 sec 0010: 3.5 sec 0011: 7 sec. 0100: 14 sec. 0101: 28 sec. 0110: 56 sec.
  • Page 34 PRELIMINARY CY82C599 CY82C599 Pin Descriptions PCI Interface Name Pin Number Description AD[31:0] 120, 122 128, PCI Address and Data bus. During the address phase, AD[31:0] contain a physical 131 138, address. During data phase, it contains 32 bit data. 152 160, 3 9...
  • Page 35 PRELIMINARY CY82C599 CPU Interface Name Pin Number Description Address bit 31 A[27:2] 15, 19, 21 25, Address bit 27 to 2 27 36, 38 40, 42 43, 45 47, 44 SLOWCLK/A28 Slow down clock signal. As and output, it can be used to control clock generator to /QPD slow down 486 CPU clock if power saving feature is supported.
  • Page 36 121, and 146 1, 14, 37, 50, 70, Ground 81, 92, 102, 112, 130, and 150 CY82C599 DC Characteristics Maximum Ratings (Abovewhichtheusefullifemaybeimpaired.Foruserguidelines, Ambient Storage Temperature ... . C to 125 not tested.)
  • Page 37 PRELIMINARY CY82C599 Switching Characteristics CY82C599 Parameter Description Min. Max. Unit CPU CLOCK TIMING CPUCLK Period CPUCLK HIGH time at 2.0V CPUCLK LOW time at 0.8V CPUCLK rise time CPUCLK fall time PCI CLOCK TIMING PCICLK Period PCICLK HIGH time at 2.0V PCICLK LOW time at 0.8V...

  • Page 38: Switching Waveforms

    PRELIMINARY CY82C599 Switching Waveforms CPUCLK Timing T100 T101 T102 2.0 v CPUCLK 1.5 v 0.8 v 82C599 2 T103 T104 PCICLK Timing T200 T201 T202 2.0 v PCICLK 1.5 v 0.8 v 82C599 2 T203 T204...
  • Page 39 PRELIMINARY CY82C599 Switching Waveforms (continued) PCI BUS INTERFACE TIMING PCICLK T401 T400 VALID DATA 82C599 2 14 PCICLK VALID DATA 82C599 2 13...
  • Page 40 PRELIMINARY CY82C599 Switching Waveforms (continued) CPU BUS INTERFACE TIMING CPUCLK T301 T300 VALID DATA 82C599 2 16 CPUCLK T303 T302 VALID DATA 82C599 2 15...
  • Page 41 PRELIMINARY CY82C599 Switching Waveforms (continued) CPU Master Read PCI Target (PCICLK) CPUCLK ADDRESS & STATUS DATA VALID VALID CPURDY LDEV FRAME IRDY DEVSEL TRDY STOP C/BE 82C599 2 17 SLOWEST READ CYCLE FASTEST CYCLE WITH WITH FASTEST TARGET FASTEST TARGET...
  • Page 42 PRELIMINARY CY82C599 Switching Waveforms (continued) CPU Master Write PCI Target (PCICLK) CPUCLK ADDRESS & STATE DATA CPURDY LDEV FRAME IRDY DEVSEL TRDY STOP C/BE 82C599 2 18 SLOWEST WRITE CYCLE FASTEST WRITE CYCLE WITH FASTEST TARGET WITH FASTEST TARGET...
  • Page 43 PRELIMINARY CY82C599 (continued) Switching Waveforms CPU Master Post Write to PCI Target, CPU side, Buffer available. CPUCLK ADDRESS & STATE DATA CPURDY LDEV ADDRESS 1WS ADDRESS 1WS ADDRESS 0WS ADDRESS 0WS DATA 1WS DATA 0WS DATA 1WS DATA 0WS 82C599 2 19...
  • Page 44 PRELIMINARY CY82C599 Switching Waveforms (continued) CPU Master Burst Post Write, to PCI Target (PCI side) Data Available in Buffer. PCICLK FRAME IRDY DEVSEL TRDY STOP A D0 D1 A D0 D1 C BE0 BE1 C BE0 BE1 C/BE 1WS BURST WRITE...
  • Page 45 PRELIMINARY CY82C599 Switching Waveforms (continued) CPU Master Read/Write to PCI Bus Miss" Cycle, Stand Alone Mode (to CPU without claiming the same cycle) CPUCLK (PCICLK) ADDRESS & STATE LDEV CPURDY BOFF FRAME IRDY DEVSEL HIGH TRDY/STOP HIGH 82C599 2 21...
  • Page 46 PRELIMINARY CY82C599 Switching Waveforms Switching Waveforms (continued) (continued) CPU Master to PCI Bus Master Abort" CPU Master to PCI Bus Master Abort" (DEVSEL) Time Out Timing (DEVSEL) Time Out Timing PCICLK PCICLK FRAME FRAME IRDY IRDY HIGH HIGH DEVSEL DEVSEL...
  • Page 47 PRELIMINARY CY82C599 (continued) Switching Waveforms CPU Master I/O Read/Write to 22/23H location, Stand Alone mode CPUCLK ADDRESS M/IO CPURDY LDEV TO NON 82C599 C.R. INDEX TO 82C599 C.R. INDEX 82C599 2 26...
  • Page 48 PRELIMINARY CY82C599 Switching Waveforms (continued) PCI Master Read From 82C599 Target (CPULK) PCICLK FRAME IRDY DEVSEL TRDY/STOP C/BE ADDRESS & STATUS DATA CPURDY FASTEST PCI MASTER FASTEST PCI MASTER WRITE TO SLOWEST WRITE TO FASTEST 82C599 SETTING WITH 82C599 SETTING WITH...
  • Page 49 PRELIMINARY CY82C599 Switching Waveforms (continued) PCI Master Write to 82C599 Target (CPUCLK) PCICLK FRAME IRDY DEVSEL TRDY C/BE Address & StATUS Data CPURDY FASTEST PCI MASTER FASTEST PCI MASTER WRITE TO SLOWEST WRITE TO FASTEST 82C599 SETTING WITH 82C599 SETTING WITH...
  • Page 50 PRELIMINARY CY82C599 Switching Waveforms (continued) PCI Master Burst Pre Read to CPU (CPUCLK) PCICLK FRAME IRDY DEVSEL TRDY HIGH STOP PCI ADDRESS 1WS DATES 1WS ADDRESS M/IO BLAST BRDY 82C599 2 29 (CPU MEMORY 3 1 1 1 MODE)
  • Page 51 PRELIMINARY CY82C599 Switching Waveforms (continued) PCI Master Burst Pre Read to CPU (CPUCLK) PCICLK FRAME IRDY DEVSEL TRDY HIGH STOP PCI ADDRESS 0WS DATA 0WS ADDRESS M/IO BLAST BRDY (CPU MEMORY 2 1 1 1 MODE) 82C599 2 30...
  • Page 52 PRELIMINARY CY82C599 (continued) Switching Waveforms PCI Master Post Write to CPU, PCI Side Buffer Available PCICLK FRAME IRDY DEVSEL TRDY/STOP ADDRESS=1WS ADDRESS=1WS ADDRESS=0WS ADDRESS=0WS DATA=1WS DATA=0WS DATA=1WS DATA=0WS 82C599 2 31 Note: CPU side same as 486 type CPU write cycle...
  • Page 53 PRELIMINARY CY82C599 (continued) Switching Waveforms I Master Burst Post Write to CPU, PCI Side Buffer Available PCICLK FRAME IRDY DEVSEL TRDY STOP ADDRESS=1WS ADDRESS=1WS ADDRESS=0WS DATA=1WS DATA=0WS DATA=0WS 82C599 2 32 Note: CPU side same as 486 type CPU write cycle.
  • Page 54 PRELIMINARY CY82C599 Switching Waveforms Switching Waveforms (continued) (continued) PCI Master Subtractive Decode DEVSEL " Timing PCI Master Subtractive Decode DEVSEL " Timing PCICLK PCICLK FRAME FRAME IRDY IRDY DEVSEL DEVSEL TRDY/ TRDY/ STOP STOP (SUB-DECODE=6PCICLK) (SUB-DECODE=5PCICLK) 82C599 2 33 82C599 2 34...
  • Page 55 PRELIMINARY CY82C599 82C599 Block Diagram 4 Level Deep FIFO CPU Bus PCI Bus Interface Interface CPU Master CPU Master CPU State Machine PCI State Machine Arbitration State Machine and Control PCI Master PCI Master CPU State Machine PCI State Machine...

  • Page 56: Package Diagrams

    Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor Corporation product. Nor does it convey or imply any license under patent or other rights. Cypress Semicon ductor does not authorize its products for use as critical components in life support systems where a malfunction or failure of the product may reasonably be expected to result in significant injury to the user.