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Type 2 (CSI-2) standard. It serves as a MIPI CSI-2-to-USB Bridge. EZ-USB CX3 is a variant of the EZ-USB FX3 device that features an integrated MIPI CSI-2 receiver mated to the general programming interface II (GPIF II). CX3 provides the ability to add SuperSpeed USB connectivity to image sensors supporting the MIPI CSI-2 interface.
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Cypress EZ-USB CX3 functional blocks, such as the CPU Subsystem, Memory, Global Controller, DMA, USB, and low-bandwidth (serial and GPIO) peripherals are available in the EZ-USB FX3 TRM. Technical terms used in this TRM are defined in the Glossary. Figure 2 is the block diagram of FX3.
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Cypress EZ-USB CX3 The differences between CX3 and FX3 devices are listed below. Table 1: Differences Between FX3 and CX3 Devices Feature Supported in FX3 Supported in CX3 P-Port Support Sync ADMux implemented with GPIF II Async SRAM implemented with GPIF II...
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Cypress EZ-USB CX3 CX3 Features CX3 supports the following features: ▪ USB 3.0 and USB 2.0 peripheral controller compliant with the USB 3.0 specification 1.0 ▪ MIPI CSI-2 RX Interface MIPI CSI-2 conformant (Version 1.01 Revision 0.04 –April 2, 2009) Supports up to four data lanes;...
Cypress EZ-USB CX3 Block Diagram is a detailed block diagram of a typical system using CX3 to transfer data from an image Figure 4 sensor to a USB Host. Figure 4: System Block Diagram USB Host Data Lanes Clock Video...
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Cypress EZ-USB CX3 MIPI CSI-2 Block Configuration APIs The MIPI CSI-2 Rx-block configuration APIs allow user applications to initialize, configure, and perform power management for the camera interface. These APIs communicate with the camera over the I C bus. For modularity, the MIPI CSI-2 configuration APIs are compiled into a separate API library (cyu3mipicsi.a).
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Cypress EZ-USB CX3 MIPI CSI-2 Block The CX3 device has an integrated MIPI CSI-2 block, which is hard-wired to the GPIF II interface on one side and provides a MIPI CSI-2 interface on the other side to interface to an image sensor that supports MIPI CSI- 2.
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Cypress EZ-USB CX3 CX3 MIPI CSI-2 Stream Formats The MIPI CSI-2 Rx block on CX3 natively supports the following stream formats and output modes: Table 3: CX3 MIPI CSI-2 Stream Formats Format CSI-2 Format and CX3 Firmware Stream Format GPIF II...
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Cypress EZ-USB CX3 Format CSI-2 Format and CX3 Firmware Stream Format GPIF II Description, Data Output Stream Mode Name Bus Width Pixel Depth Typea P[15:0] YUV422 format YUV422 Data Order: CY_U3P_CSI_DF_YUV422_8_1 16 bits per 0x1E 16-bit {U1,Y1},{V1,Y2},{ 8-bit Mode 1 pixel U3, Y3},{V3,Y4}...
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Cypress EZ-USB CX3 MIPI CSI-2 Block Clocks Figure 6 shows the CX3 clocks on the MIPI CSI-2 block. The interface takes a reference clock as its input and generates the required clocking using a PLL followed by multiple clock dividers. In the CX3 application firmware, clock configuration parameters are a part of the CyU3PMipicsiCfg_t structure, which is passed to the CyU3PMipicsiSetIntfParams() API to configure the CSI-2 block.
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Cypress EZ-USB CX3 Table 4: PLL Clock Frequency Calculation example REFCLK in MHz PLL_PRD PLL_FBD PLL_FRS PLL_CLK in MHz 19.2 19.2 19.2 484.8 19.2 78.4 19.2 403.2 1.7.3 CSI RX LP HS Clock This clock is used for detecting the CSI Link Low Power (LP) High Speed (HS) transition. It is generated by dividing the PLL_CLK by a value of 2, 4, or 8.
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Cypress EZ-USB CX3 CX3 MIPI CSI-2 Block Power Modes The MIPI CSI-2 block on CX3 supports the following power modes: ▪ Active: In this mode, the MIPI CSI-2 receiver block will be active and transfer data from the image sensor to the GPIF II interface.
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Cypress EZ-USB CX3 Fixed-Function GPIF II Interface on CX3 The fixed-function GPIF II state machine of CX3 is shown in Figure 7. This state machine makes the parallel data provided by the MIPI CSI-2 receiver available for transfer over two sockets, which can be connected to a manual, Many-to-One DMA channel.
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Cypress EZ-USB CX3 1.10 MIPI CSI-2 Block Registers The MIPI CSI-2 block exposes a set of registers used to configure the block over I C. The block is available at the 7-bit I C slave address 7'b0000111 (Read address 0x0F; Write address 0x0E). The block supports 100 kHz and 400 kHz I C operation.
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Cypress EZ-USB CX3 1.10.1 CX3_SYSTEM_CTRL (Register Address: 0x0002) This register controls the Sleep and Software Reset functionality for the MIPI CSI-2 block. This register is used by the CyU3PMipicsiSleep(), CyU3PMipicsiWakeup(), CyU3PMipicsiReset() APIs. NAME RESERVED NAME RESERVED SLEEP RESET Register Field Description RESERVED.
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Cypress EZ-USB CX3 1.10.2 CX3_CONFIG_CTRL (Register Address: 0x0004) This register controls number of data lanes and the output data mode for the MIPI CSI-2 block. This register CyU3PMipicsiSetIntfParams() queried using CyU3PMipicsiQueryIntfParams() API. NAME RESERVED DATA MODE NAME RESERVED OUTEN RESERVED...
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Cypress EZ-USB CX3 1.10.3 CX3_FIFO_CTRL (Register Address: 0x0006) This register determines the FIFO trigger level for the initiation of parallel data output from the parallel output buffer of the MIPI CSI-2 block. The MIPI CSI-2 block waits for the parallel output buffer to reach the level specified by this register before transferring data to GPIF II interface.
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Cypress EZ-USB CX3 1.10.4 CX3_DATA_FMT (Register Address: 0x0008) This register controls the output data format for the MIPI CSI-2 block. This register is set by the API and queried using the CyU3PMipicsiSetIntfParams() API. CyU3PMipicsiQueryIntfParams() NAME RESERVED NAME DATA FORMAT DATA FMT ENABLE...
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Cypress EZ-USB CX3 1.10.5 CX3_MCLK_CTRL (Register Address: 0x000C) This register configures the MCLK divider and controls the Image Sensor Reference Clock (MCLK) output from the MIPI CSI-2 block. Detailed information on calculating the MCLK value is provided in Section 1.7.5...
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Cypress EZ-USB CX3 1.10.6 CX3_CSI_SENSOR_SIG_EN (Register Address: 0x0010) This register enables or disables the output of the XSHUTDOWN and XRESET signals from the MIPI CSI-2 block. This register is set by the APIs. CyU3PMipicsiInit() CyU3PMipicsiReset() NAME RESERVED NAME RESERVED XSHUTDOWN ENABLE...
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Cypress EZ-USB CX3 1.10.7 CX3_CSI_SENSOR_SIG_VAL (Register Address: 0x0014) This register configures the drive value for the XSHUTDOWN and XRESET signals for the MIPI CSI-2 block. This register is set using the CyU3PMipicsiSetSensorControl() API. NAME RESERVED XSHUTDOWN XRESET NAME RESERVED RESERVED...
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Cypress EZ-USB CX3 1.10.8 CX3_PLL_CTRL0 (Register Address: 0x0016) This register configures the PLL clock on the MIPI CSI-2 block. Detailed description of how the PLL Clock is generated based on the values from CX3_PLL_CTRL0 (Register Address: 0x0016) CX3_PLL_CTRL1 (Register Address: 0x0018) is provided in Section 1.7.2...
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Cypress EZ-USB CX3 1.10.9 CX3_PLL_CTRL1 (Register Address: 0x0018) This register configures the PLL clock on the MIPI CSI-2 block. Detailed description of how the PLL Clock is generated based on the values from CX3_PLL_CTRL0 (Register Address: 0x0016) CX3_PLL_CTRL1 (Register Address: 0x0018) is provided in Section 1.7.2...
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Cypress EZ-USB CX3 1.10.10 CX3_CLK_CTRL (Register Address: 0x0020) This register configures the interface clock dividers for the MIPI CSI-2 block. This register CyU3PMipicsiSetIntfParams() queried using CyU3PMipicsiQueryIntfParams() API. NAME RESERVED NAME RESERVED CSI RX CLK DIV MCLK REF DIV PAR OUT CLK DIV...
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Cypress EZ-USB CX3 1.10.11 CX3_BYTE_COUNT (Register Address: 0x0022) This register configures the byte count per active line for the MIPI CSI-2 block. This register CyU3PMipicsiSetIntfParams() queried using CyU3PMipicsiQueryIntfParams() API. NAME BYTE COUNT [15:8] TYPE NAME BYTE COUNT [7:0] TYPE Register Field...
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Cypress EZ-USB CX3 1.10.12 CX3_PHY_TIME_DELAY (Register Address: 0x0060) This register configures delay parameters for the MIPI CSI-2 Receiver PHY on the CX3 MIPI CSI-2 block. The settings depend on the CSI_RX_CLK defined in 1.7.3 This register CyU3PMipicsiSetIntfParams() queried using CyU3PMipicsiQueryIntfParams() API.
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Cypress EZ-USB CX3 1.11 CX3 MIPI CSI-2 APIs This section details the APIs exposed by the EZ USB FX3 SDK to configure and utilize the MIPI CSI-2 block on the CX3. Additional details on the APIs and the enumerations and structure types used by them can be...
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Cypress EZ-USB CX3 CX3_CSI_SENSOR_SIG_VAL register in its default state (0x0000) thereby setting the MIPI XRESET and XSHUTDOWN signals as Drive 0. If either of these signals, needs to be in Drive 1 state for sensor operation, it needs to be explicitly set to Drive 1 state using...
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Detailed usage instructions for the configuration tool are available as part of the EZ-USB Suite help menus and as part of the Cypress EZ-USB FX3 Quick Start Guide (Getting Started with FX3 SDK.pdf) available in the doc folder of the EZ-USB FX3 SDK installation path.
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Cypress EZ-USB CX3 1.11.10 CyU3PMipicsiQueryIntfParams() CyU3PReturnStatus_t CyU3PMipicsiQueryIntfParams (CyU3PMipicsiCfg_t * csiCfg) This function is used to read back the MIPI-CSI interface parameters from the block. The parameters read back are provided to the calling function via the pointer of type CyU3PMipicsiCfg_t passed in from the calling function.
Additional information on the CX3 including Datasheets and Application notes can be found at http://www.cypress.com/cx3/. Additional information on the FX3 including Datasheets, Application notes and the EZ-USB FX3 Technical Reference Manual (TRM) can be found at http://www.cypress.com/fx3/. The EZ-USB FX3 SDK software download and documentation provided as part of the SDK (Programmers Manual,...
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Cypress EZ-USB CX3 1.13 Glossary Application Programming Interface. A series of software routines that comprise an interface between an application and lower-level services and functions (for example interfaces to configure and control the FX3/CX3 device operation). EZ-USB FX3 SDK provides a set of libraries which provide APIs to configure and control the operation of the FX3 device.
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Cypress EZ-USB CX3 Motion-JPEG or MJPEG is a video format in which each video frame is separately MJPEG Format compressed using the JPEG still-image compression algorithm. A sequence of such frames represents the source video. A pixel is the smallest controllable element of a picture represented on the screen. Each pixel is a sample of an original image;...
Uses”). A critical component is any component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products.
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