Adc Left Channel Gain (Address 1Ch); Adc Right Channel Gain (Address 1Dh); Receiver Mode Control (Address 1Eh); Table 18. Example Adc Input Gain Settings - Cirrus Logic CS42518-CQZ Instructions Manual

6.16

ADC Left Channel Gain (address 1Ch)

7 6
Reserved Reserved
6.16.1 ADC LEFT CHANNEL GAIN (LGAINX)
Default = 00h
Function:
The level of the left analog channel can be adjusted in 1 dB increments as dictated by the Soft and
Zero Cross bits (SZC[1:0]) from +15 to -15 dB. Levels are decoded in two's complement, as shown
in Table 18.
6.17

ADC Right Channel Gain (address 1Dh)

7 6
Reserved Reserved
6.17.1 ADC RIGHT CHANNEL GAIN (RGAINX)
Default = 00h
Function:
The level of the right analog channel can be adjusted in 1 dB increments as dictated by the Soft and
Zero Cross bits (SZC[1:0]) from +15 to -15 dB. Levels are decoded in two's complement, as shown
in Table 18.
6.18

Receiver Mode Control (address 1Eh)

7 6
SP_SYNC Reserved
6.18.1 SERIAL PORT SYNCHRONIZATION (SP_SYNC)
Default = 0
0 - CX & SAI Serial Port timings not in phase
1 - CX & SAI Serial Port timings are in phase
Function:
Forces the LRCK and SCLK from the CX & SAI Serial Ports to align and operate in phase. This func-
tion will operate when both ports are running at the same sample rate or when operating at different
sample rates.
5 4
LGAIN5 LGAIN4
5 4
RGAIN5 RGAIN4
Binary Code Decimal Value
001111
001010
000101
000000
111011
110110
110001

Table 18. Example ADC Input Gain Settings

5 4
DE-EMPH1 DE-EMPH0
3
LGAIN3 LGAIN2
3
RGAIN3 RGAIN2
Volume Setting
+15 +15 dB
+10 +10 dB
+5 +5 dB
0 0 dB
-5 -5 dB
-10 -10 dB
-15 -15 dB
3
INT1 INT0
CS42518
2 1
LGAIN1
2 1
RGAIN1
2 1
HOLD1
0
LGAIN0
0
RGAIN0
0
HOLD0
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