Cirrus Logic CS42518-CQZ Instructions Manual page 3

4.3.4 ATAPI Specification ............................................................................................ 23
4.4. S/PDIF Receiver ............................................................................................................. 24
4.4.1 8:2 S/PDIF Input Multiplexer ............................................................................... 24
4.4.2 Error Reporting and Hold Function ..................................................................... 24
4.4.3 Channel Status Data Handling ............................................................................ 24
4.4.4 User Data Handling ............................................................................................. 24
4.4.5 Non-Audio Auto-Detection .................................................................................. 24
4.5. Clock Generation ............................................................................................................ 25
4.5.1 PLL and Jitter Attenuation ................................................................................... 25
4.5.2 OMCK System Clock Mode ................................................................................ 26
4.5.3 Master Mode ....................................................................................................... 26
4.5.4 Slave Mode ......................................................................................................... 26
4.6. Digital Interfaces ............................................................................................................. 27
4.6.1 Serial Audio Interface Signals ............................................................................. 27
4.6.2 Serial Audio Interface Formats ........................................................................... 29
4.6.3 ADCIN1/ADCIN2 Serial Data Format ................................................................. 32
4.6.4 One Line Mode(OLM) Configurations ................................................................. 33
4.6.4a OLM Config #1 ..................................................................................... 33
4.6.4b OLM Config #2 ..................................................................................... 34
4.6.4c OLM Config #3 ..................................................................................... 35
4.6.4d OLM Config #4 ..................................................................................... 36
4.6.4e OLM Config #5 ..................................................................................... 37
4.7. Control Port Description and Timing ............................................................................... 38
4.7.1 SPI Mode ............................................................................................................ 38
4.7.2 I2C Mode ............................................................................................................ 39
4.8. Interrupts ........................................................................................................................ 40
4.9. Reset and Power-up ...................................................................................................... 40
4.10. Power Supply, Grounding, and PCB layout .................................................................. 40
5 REGISTER QUICK REFERENCE ........................................................................................... 42
6 REGISTER DESCRIPTION ..................................................................................................... 46
6.1 Memory Address Pointer (MAP) ....................................................................................... 46
6.2 Chip I.D. and Revision Register (address 01h) (Read Only) ............................................ 46
6.3 Power Control (address 02h)............................................................................................ 47
6.4 Functional Mode (address 03h) ........................................................................................ 47
6.5 Interface Formats (address 04h) ...................................................................................... 49
6.6 Misc Control (address 05h) .............................................................................................. 51
6.7 Clock Control (address 06h) ............................................................................................. 52
6.8 OMCK/PLL_CLK Ratio (address 07h) (Read Only) ......................................................... 54
6.9 RVCR Status (address 08h) (Read Only)......................................................................... 54
6.10 Burst Preamble PC and PD Bytes (addresses 09h - 0Ch)(Read Only).......................... 55
6.11 Volume Transition Control (address 0Dh) ...................................................................... 56
6.12 Channel Mute (address 0Eh).......................................................................................... 58
6.13 Volume Control (addresses 0Fh, 10h, 11h, 12h, 13h, 14h, 15h, 16h)
6.14 Channel Invert (address 17h) ......................................................................................... 58
6.15 Mixing Control Pair 1 (Channels A1 & B1)(address 18h)
Mixing Control Pair 2 (Channels A2 & B2)(address 19h)
Mixing Control Pair 3 (Channels A3 & B3)(address 1Ah)
Mixing Control Pair 4 (Channels A4 & B4)(address 1Bh) ............................................ 59
6.16 ADC Left Channel Gain (address 1Ch) .......................................................................... 61
6.17 ADC Right Channel Gain (address 1Dh) ........................................................................ 61
6.18 Receiver Mode Control (address 1Eh) ........................................................................... 61
6.19 Receiver Mode Control 2 (address 1Fh) ........................................................................ 62
6.20 Interrupt Status (address 20h) (Read Only) ................................................................... 63
CS42518
........................ 58
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