Switching Characteristics - Control Port - Spi Format; Figure 4. Control Port Timing - Spi Format - Cirrus Logic CS42518-CQZ Instructions Manual

SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT

(For CQ, T = -10 to +70° C; For DQ, T
A
Inputs: Logic 0 = DGND, Logic 1 = VLC, C
CCLK Clock Frequency
CS High Time Between Transmissions
CS Falling to CCLK Edge
CCLK Low Time
CCLK High Time
CDIN to CCLK Rising Setup Time
CCLK Rising to DATA Hold Time
CCLK Falling to CDOUT Stable
Rise Time of CDOUT
Fall Time of CDOUT
Rise Time of CCLK and CDIN
Fall Time of CCLK and CDIN
Notes: 19. If Fs is lower than 46.875 kHz, the maximum CCLK frequency should be less than 128 Fs. This is
dictated by the timing requirements necessary to access the Channel Status and User Bit buffer
memory. Access to the control register file can be carried out at the full 6 MHz rate. The minimum
allowable input sample rate is 8 kHz, so choosing CCLK to be less than or equal to 1.024 MHz should
be safe for all possible conditions.
20. Data must be held for sufficient time to bridge the transition time of CCLK.
21. For f <1 MHz.
sck
14
= -40 to +85° C; VA=VARX = 5 V, VD =VLS= 3.3 V; VLC = 1.8 V to 5.25 V;
A
= 30 pF)
L
Parameter
CS
t css
CCLK
t r2
CDIN
t dsu
CDOUT

Figure 4. Control Port Timing - SPI Format

Symbol
(Note 19) f
sck
t
csh
t
css
t
scl
t
sch
t
dsu
(Note 20) t
dh
t
pd
t
r1
t
f1
(Note 21) t
r2
(Note 21) t
f2
t scl t sch
t f2
t dh
t pd
CS42518
Min Typ Max
0 - 6.0
1.0 - -
20 - -
66 - -
66 - -
40 - -
15 - -
- - 50
- - 25
- - 25
- - 100
- - 100
t csh
Units
MHz
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns