Cirrus Logic CS42518-CQZ Instructions Manual page 5

CS42518
LIST OF FIGURES
Figure 1. Serial Audio Port Master Mode Timing .......................................................................... 12
Figure 2. Serial Audio Port Slave Mode Timing ............................................................................ 12
Figure 3. Control Port Timing - I2C Format................................................................................... 13
Figure 4. Control Port Timing - SPI Format................................................................................... 14
Figure 5. Typical Connection Diagram.......................................................................................... 19
Figure 6. Typical Connection Diagram with PLL ........................................................................... 20
Figure 7. Full-Scale Analog Input.................................................................................................. 21
Figure 8. Full-Scale Output ........................................................................................................... 22
Figure 9. ATAPI Block Diagram (x = channel pair 1, 2, 3, 4) ........................................................ 23
Figure 10. CS42518 Clock Generation ......................................................................................... 25
2
Figure 11. I S Serial Audio Formats ............................................................................................. 29
Figure 12. Left Justified Serial Audio Formats .............................................................................. 30
Figure 13. Right Justified Serial Audio Formats............................................................................ 30
Figure 14. One Line Mode #1 Serial Audio Format....................................................................... 31
Figure 15. One Line Mode #2 Serial Audio Format....................................................................... 31
Figure 16. ADCIN1/ADCIN2 Serial Audio Format......................................................................... 32
Figure 17. OLM Configuration #1.................................................................................................. 33
Figure 18. OLM Configuration #2.................................................................................................. 34
Figure 19. OLM Configuration #3.................................................................................................. 35
Figure 20. OLM Configuration #4.................................................................................................. 36
Figure 21. OLM Configuration #5.................................................................................................. 37
Figure 22. Control Port Timing in SPI Mode ................................................................................. 38
Figure 23. Control Port Timing, I2C Write ..................................................................................... 39
Figure 24. Control Port Timing, I2C Read ..................................................................................... 39
Figure 25. Recommended Analog Input Buffer............................................................................. 74
Figure 26. Recommended Analog Output Buffer .......................................................................... 74
Figure 27. Channel Status Data Buffer Structure.......................................................................... 76
Figure 28. PLL Block Diagram ...................................................................................................... 78
Figure 29. Jitter Attenuation Characteristics of PLL...................................................................... 79
Figure 30. Recommended Layout Example.................................................................................. 80
Figure 31. Consumer Input Circuit ................................................................................................ 81
Figure 32. S/PDIF MUX Input Circuit ............................................................................................ 81
Figure 33. TTL/CMOS Input Circuit............................................................................................... 81
Figure 34. Single Speed Mode Stopband Rejection ..................................................................... 82
Figure 35. Single Speed Mode Transition Band ........................................................................... 82
Figure 36. Single Speed Mode Transition Band (Detail)............................................................... 82
Figure 37. Single Speed Mode Passband Ripple ......................................................................... 82
Figure 38. Double Speed Mode Stopband Rejection.................................................................... 82
Figure 39. Double Speed Mode Transition Band .......................................................................... 82
Figure 40. Double Speed Mode Transition Band (Detail) ............................................................. 83
Figure 41. Double Speed Mode Passband Ripple ........................................................................ 83
Figure 42. Quad Speed Mode Stopband Rejection ...................................................................... 83
Figure 43. Quad Speed Mode Transition Band............................................................................. 83
Figure 44. Quad Speed Mode Transition Band (Detail) ................................................................ 83
Figure 45. Quad Speed Mode Passband Ripple........................................................................... 83
Figure 46. Single Speed (fast) Stopband Rejection ...................................................................... 84
Figure 47. Single Speed (fast) Transition Band ............................................................................ 84
Figure 48. Single Speed (fast) Transition Band (detail) ................................................................ 84
Figure 49. Single Speed (fast) Passband Ripple .......................................................................... 84
Figure 50. Single Speed (slow) Stopband Rejection..................................................................... 84
Figure 51. Single Speed (slow) Transition Band........................................................................... 84
5