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110 dB, 192 kHz 8-Ch Codec with S/PDIF Receiver
Features
Eight 24-bit D/A, two 24-bit A/D Converters
110 dB DAC / 114 dB ADC Dynamic Range
-100 dB THD+N
System Sampling Rates up to 192 kHz
S/PDIF Receiver compatible with EIAJ
CP1201 and IEC-60958
Recovered S/PDIF CLK or System Clock
Selection
8:2 S/PDIF Input MUX
ADC High Pass Filter for DC Offset
Calibration
Expandable ADC Channels and One-line-
Mode Support
Digital Output Volume control with soft ramp
Digital +/-15dB Input Gain Adjust for ADC
Differential Analog Architecture
Supports logic levels between 5 V and 1.8 V
RXP1/G PO1
RXP2/GPO2
RXP3/G PO 3
RXP4/GPO4
RXP5/G PO5
RXP6/GPO6
RXP7/GPO7
Preliminary Product Information
Cirrus Logic, Inc.
http://www.cirrus.com
VARX
AGND
TXP
RXP0
C lock/Data
Rx
Recovery
GPO
M UTEC
MUT E
FILT+
VQ
Ref
REFGND
VA
AG ND
AINL+
ADC#1
AINL-
AINR+
ADC#2
AINR-
AO UTA1+
AOUTA1-
AOUT B1+
AOUTB1-
AOUT A2+
AOUTA2-
AOUTB2+
AO UTB2-
AOUT A3+
AOUTA3-
AOUT B3+
AOUTB3-
AOUTA4+
AO UTA4-
AOUTB4+
AOUTB4-
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Copyright
General Description
The CS42518 codec provides two analog-to-digital and eight
digital-to-analog delta-sigma converters, as well as an integrat-
ed S/PDIF receiver, in a 64-pin LQFP package.
The CS42518 integrated S/PDIF receiver supports up to eight
inputs, clock recovery circuitry and format auto-detection. The
internal stereo ADC is capable of independent channel gain
control for single-ended or differential analog inputs. All eight
channels of DAC provide digital volume control and differential
analog outputs. The general purpose outputs may be driven
high or low, or mapped to a variety of DAC mute controls or
ADC overflow indicators.
The CS42518 is ideal for audio systems requiring wide dynam-
ic range, negligible distortion and low noise, such as A/V
receivers, DVD receivers, digital speaker and automotive audio
systems.
ORDERING INFORMATION
CS42518-CQ
CS42518-CQZ
CS42518-DQZ
CDB42518
LPFLT
DGND
DGND VD
C&U Bit
Data Buffer
S/PDIF
Decoder
Format
Detector
Internal MCLK
DEM
Digital F ilter
G ain & Clip
ADC
Serial
Data
Digital Filter
Gain & Clip
DAC#1
DAC#2
DAC#3
DAC#4
DAC#5
DAC#6
DAC#7
DAC#8
Cirrus Logic, Inc. 2004
(All Rights Reserved)
CS42518
-10° to 70° C
64-pin LQFP
-10° to 70° C
64-pin LQFP
-40° to 85° C
64-pin LQFP
Evaluation Board
VD
INT
RST
Control
AD0/CS
Port
AD1/CDIN
SDA/C DOUT
SCL/CCLK
VLC
OM CK
Mult/Div
RM CK
Serial
SAI_LRCK
Audio
SAI_SCLK
Interface
SAI_SDOUT
Port
VLS
ADCIN1
ADC IN2
CX_SDO UT
CX_LR CK
CX_SCLK
CX_SDIN1
CX_SDIN2
CX_SDIN 3
CODEC
Serial
CX_SDIN4
Port
JUL '04
DS584PP4
1
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Table of Contents
Related Manuals for Cirrus Logic CS42518-CQZ
Summary of Contents for Cirrus Logic CS42518-CQZ
- Page 1 AO UTA4- AOUTB4+ DAC#8 AOUTB4- This document contains information for a new product. Preliminary Product Information Cirrus Logic reserves the right to modify this product without notice. Cirrus Logic, Inc. http://www.cirrus.com Copyright Cirrus Logic, Inc. 2004 JUL ‘04 (All Rights Reserved)
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Page 2: Table Of Contents
C Patent Rights to use those components in a standard I C system. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. - Page 3 CS42518 4.3.4 ATAPI Specification .................... 23 4.4. S/PDIF Receiver ......................24 4.4.1 8:2 S/PDIF Input Multiplexer ................24 4.4.2 Error Reporting and Hold Function ..............24 4.4.3 Channel Status Data Handling ................24 4.4.4 User Data Handling ..................... 24 4.4.5 Non-Audio Auto-Detection .................. 24 4.5.
- Page 4 CS42518 6.21 Interrupt Mask (address 21h)..................64 6.22 Interrupt Mode MSB (address 22h) Interrupt Mode LSB (address 23h)................64 6.23 Channel Status Data Buffer Control (address 24h) ............65 6.24 Receiver Channel Status (address 25h) (Read Only)............. 65 6.25 Receiver Errors (address 26h) (Read Only) ..............66 6.26 Receiver Errors Mask (address 27h) ................
- Page 5 CS42518 LIST OF FIGURES Figure 1. Serial Audio Port Master Mode Timing ................12 Figure 2. Serial Audio Port Slave Mode Timing ................12 Figure 3. Control Port Timing - I2C Format................... 13 Figure 4. Control Port Timing - SPI Format................... 14 Figure 5.
- Page 6 CS42518 Figure 52. Single Speed (slow) Transition Band (detail) ............... 85 Figure 53. Single Speed (slow) Passband Ripple ................. 85 Figure 54. Double Speed (fast) Stopband Rejection ..............85 Figure 55. Double Speed (fast) Transition Band ................85 Figure 56. Double Speed (fast) Transition Band (detail) ............... 85 Figure 57.
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Page 7: Characteristics And Specifications
CS42518 1 CHARACTERISTICS AND SPECIFICATIONS (All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical per- formance characteristics and specifications are derived from measurements taken at nominal supply voltages and = 25° C.) SPECIFIED OPERATING CONDITIONS (AGND=DGND=0, all voltages with respect to ground; OMCK=12.288 MHz;... -
Page 8: Analog Input Characteristics
CS42518 ANALOG INPUT CHARACTERISTICS = 25° C; VA =VARX= 5 V, VD = 3.3 V, Logic "0" = DGND =AGND = 0 V; Logic "1" = VLS = VLC = 5 V; Measurement Bandwidth is 10 Hz to 20 kHz unless otherwise specified. -
Page 9: A/D Digital Filter Characteristics
CS42518 FILT+ Nominal Voltage Ω Output Impedance Maximum allowable DC current 0.01 0.01 Notes: 3. Referred to the typical full-scale voltage. 4. Measured between AIN+ and AIN- A/D DIGITAL FILTER CHARACTERISTICS Parameter Symbol Unit Single Speed Mode (2 to 50 kHz sample rates) Passband (-0.1 dB) (Note 5) -
Page 10: Analog Output Characteristics
CS42518 ANALOG OUTPUT CHARACTERISTICS = 25° C; VA =VARX= 5 V, VD = 3.3 V, Logic "0" = DGND =AGND = 0 V; Logic "1" = VLS = VLC = 5V; Measurement Bandwidth 10 Hz to 20 kHz unless otherwise specified.;... -
Page 11: D/A Digital Filter Characteristics
CS42518 D/A DIGITAL FILTER CHARACTERISTICS Fast Roll-Off Slow Roll-Off Parameter Unit Combined Digital and On-chip Analog Filter Response - Single Speed Mode - 48 kHz Passband (Note 9) to -0.01 dB corner 0.4535 0.4166 to -3 dB corner 0.4998 0.4998 Frequency Response 10 Hz to 20 kHz -0.01 +0.01... -
Page 12: Switching Characteristics
CS42518 SWITCHING CHARACTERISTICS (For CQ, T = -10 to +70° C; For DQ, T = -40 to +85° C; VA=VARX = 5 V, VD =VLC= 3.3 V, VLS = 1.8 V to 5.25 V; Inputs: Logic 0 = DGND, Logic 1 = VLS, C = 30 pF) Parameters Symbol... -
Page 13: Switching Characteristics - Control Port - I2C Format
CS42518 SWITCHING CHARACTERISTICS - CONTROL PORT - I C FORMAT (For CQ, T = -10 to +70° C; For DQ, T = -40 to +85° C; VA=VARX = 5 V, VD =VLS= 3.3 V; VLC = 1.8 V to 5.25 V; Inputs: Logic 0 = DGND, Logic 1 = VLC, C = 30 pF) Parameter... -
Page 14: Switching Characteristics - Control Port - Spi Format
CS42518 SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT (For CQ, T = -10 to +70° C; For DQ, T = -40 to +85° C; VA=VARX = 5 V, VD =VLS= 3.3 V; VLC = 1.8 V to 5.25 V; Inputs: Logic 0 = DGND, Logic 1 = VLC, C = 30 pF) Parameter... -
Page 15: Dc Electrical Characteristics
CS42518 DC ELECTRICAL CHARACTERISTICS = 25° C; AGND=DGND=0, all voltages with respect to ground; OMCK=12.288 MHz; Master Mode) Parameter Symbol Units Power Supply Current normal operation, VA = VARX = 5 V (Note 22) VD = 5 V VD = 3.3 V µA Interface current, VLC=5 V (Note 23) µA... -
Page 16: Pin Descriptions
CS42518 2 PIN DESCRIPTIONS 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 CX_SDIN1 RXP1/G PO 1 CX _SCLK RXP2/G PO 2 CX_LRCK RXP3/G PO 3 RXP4/G PO 4 DG ND RXP5/G PO 5 RXP6/G PO 6 SCL/CCLK RXP7/G PO 7... - Page 17 CS42518 AD0/CS Address Bit 0 (I C)/Control Port Chip Select (SPI) (Input ) - AD0 is a chip address pin in I C mode; CS is the chip select signal in SPI mode. Interrupt (Output ) - The CS42518 will generate an interrupt condition as per the Interrupt Mask register. See “Interrupts”...
- Page 18 CS42518 CX_SDOUT CODEC Serial Data Output ( Output ) - Output for two’s complement serial audio data from the internal and external ADCs. External ADC Serial Input ( Input ) - The CS42518 provides for up to two external stereo analog to digital ADCIN1 ADCIN2 converter inputs to provide a maximum of six channels on one serial data output line when the CS42518...
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Page 19: Typical Connection Diagrams
CS42518 3 TYPICAL CONNECTION DIAGRAMS + 3.3 V to +5 V +5 V 0 .0 1 µ F 0 .1 µ F 0.1 µ F 0 .01 µ F 10 µ F 1 0 µ F 0 .0 1 µ F 0 .1 µ... -
Page 20: Figure 6. Typical Connection Diagram With Pll
CS42518 +3.3 V to +5 V +5 V 0.01 µF 0.1 µF 0.1 µF 0.01 µF 10 µF 10 µF 0.01 µF 0.1 µF 0.1 µF 0.01 µF 10 µF 10 µF Analog Output Buffer AOUTA1+ Driver AOUTA1- Mute Circuit (optional) RXP0 S/PDIF RXP1/GPO1... -
Page 21: Applications
CS42518 4 APPLICATIONS 4.1. Overview The CS42518 is a highly integrated mixed signal 24-bit audio codec comprised of 2 analog-to-digital con- verters (ADC), implemented using multi-bit delta-sigma techniques, 8 digital-to-analog converters (DAC) and a 192 kHz digital audio S/PDIF receiver. Other functions integrated within the codec include indepen- dent digital volume controls for each DAC, digital de-emphasis filters for DAC and S/PDIF, digital gain control for ADC channels, ADC high-pass filters, an on-chip voltage reference, and an 8:2 mux for S/PDIF sources. -
Page 22: High Pass Filter And Dc Offset Calibration
CS42518 4.2.2 High Pass Filter and DC Offset Calibration The high pass filter continuously subtracts a measure of the DC offset from the output of the decimation filter. The high pass filter can be independently enabled and disabled. If the HPF_Freeze bit is set during normal operation, the current value of the DC offset for the corresponding channel is frozen and this DC offset will continue to be subtracted from the conversion result. -
Page 23: Digital Volume And Mute Control
CS42518 4.3.3 Digital Volume and Mute Control Each DAC’s output level is controlled via the Volume Control registers operating over the range of 0 to -127 dB attenuation with 0.5 dB resolution. See “Volume Control (addresses 0Fh, 10h, 11h, 12h, 13h, 14h, 15h, 16h)”... -
Page 24: S/Pdif Receiver
CS42518 4.4. S/PDIF Receiver The CS42518 includes an S/PDIF digital audio receiver. The S/PDIF receiver accepts and decodes digital audio data according to the IEC60958 (S/PDIF), and EIAJ CP-1201 interface standards. The receiver con- sists of an 8:2 multiplexer input stage driven through pins RXP0 and RXP1/GPO1 - RXP7/GPO7, a PLL based clock recovery circuit, and a decoder which separates the audio data from the channel status and user data. -
Page 25: Clock Generation
CS42518 4.5. Clock Generation The clock generation for the CS42518 is shown in the figure below. The internal MCLK is derived from the output of the PLL or a master clock source attached to OMCK. The mux selection is controlled by the SW_CTRLx bits and can be configured to manual switch mode only, or automatically switch on loss of PLL lock to the other source input. -
Page 26: Omck System Clock Mode
CS42518 4.5.2 OMCK System Clock Mode A special clock switching mode is available that allows the clock that is input through the OMCK pin to be used as the internal master clock. This feature is controlled by the SW_CTRLx bits in register “Clock Con- trol (address 06h)”... -
Page 27: Digital Interfaces
CS42518 Line Mode #2 is not supported. Refer to Table 4 for required clock ratios. The sample rate to OMCK ratios and OMCK frequency requirements for Slave mode operation are shown in Table 2. Single Speed Double Speed Quad Speed One Line Mode #1 OMCK/LRCK Ratio 256x, 384x, 512x... - Page 28 CS42518 Serial Inputs / Outputs CX_SDIN3 left channel DAC #5 right channel DAC #6 one line mode not used CX_SDIN4 left channel DAC #7 right channel DAC #8 one line mode DAC channels 7,8 CX_SDOUT left channel ADC #1 right channel ADC #2 one line mode ADC channels 1,2,3,4,5,6...
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Page 29: Serial Audio Interface Formats
CS42518 4.6.2 Serial Audio Interface Formats The CODEC_SP and SAI_SP digital audio serial ports support 5 formats with varying bit depths from 16 to 24 as shown in Figures 11 to 15. These formats are selected using the configuration bits in the regis- ters, “Functional Mode (address 03h)”... -
Page 30: Figure 12. Left Justified Serial Audio Formats
CS42518 CX_LRCK Left Channel Right Channel SAI_LRCK CX_SCLK SAI_SCLK CX_SDINx -1 -2 -3 -4 -5 +5 +4 +3 +2 +1 -1 -2 -3 -4 +5 +4 +3 +2 +1 CX_SDOUT SAI_SDOUT Left Justified Mode, Data Valid on Rising Edge of SCLK Bits/Sample SCLK Rate(s) Notes... -
Page 31: Figure 14. One Line Mode #1 Serial Audio Format
CS42518 64 clks 64 clks CX_LRCK SAI_LRCK Left Channel Right Channel CX_SCLK SAI_SCLK CX_SDIN1 DAC1 DAC3 DAC5 DAC2 DAC4 DAC6 20 clks 20 clks 20 clks 20 clks 20 clks 20 clks DAC7 DAC8 CX_SDIN4 20 clks 20 clks ADC1 ADC3 ADC5 ADC2... -
Page 32: Adcin1/Adcin2 Serial Data Format
CS42518 4.6.3 ADCIN1/ADCIN2 Serial Data Format The two serial data lines which interface to the optional external ADCs, ADCIN1 and ADCIN2, support only left-justified, 24-bit samples at 64Fs or 128Fs. This interface is not affected by any of the serial port configuration register bit settings. -
Page 33: One Line Mode(Olm) Configurations
CS42518 4.6.4 One Line Mode(OLM) Configurations 4.6.4a OLM Config #1 One Line Mode Configuration #1 can support up to 8 channels of DAC data, 6 channels of ADC data and 2 channels of S/PDIF received data. This is the only configuration which will support up to 24-bit samples at a sampling frequency of 48 kHz on all channels for both the DAC and ADC. -
Page 34: Olm Config #2
CS42518 4.6.4b OLM Config #2 This configuration will support up to 8 channels of DAC data, 6 channels of ADC data and no channels of S/PDIF received data and will handle up to 20-bit samples at a sampling frequency of 96 kHz on all chan- nels for both the DAC and ADC. -
Page 35: Olm Config #3
CS42518 4.6.4c OLM Config #3 This One Line Mode configuration #3 will support up to 8 channels of DAC data, 6 channels of ADC data and 2 channels of S/PDIF received data and will handle up to 20-bit samples at a sampling frequency of 48 kHz on all channels for both the DAC and ADC. -
Page 36: Olm Config #4
CS42518 4.6.4d OLM Config #4 This configuration will support up to 8 channels of DAC data, 6 channels of ADC data and no channels of S/PDIF received data. OLM Config #4 will handle up to 20-bit ADC samples at an Fs of 48 kHz and 24-bit DAC samples at an Fs of 48 kHz. -
Page 37: Olm Config #5
CS42518 4.6.4e OLM Config #5 This One-Line Mode configuration can support up to 8 channels of DAC data, 2 channels of ADC data and 2 channels of S/PDIF received data and will handle up to 24-bit samples at a sampling frequency of 48 kHz on all channels for both the DAC and ADC. -
Page 38: Control Port Description And Timing
CS42518 4.7. Control Port Description and Timing The control port is used to access the registers, allowing the CS42518 to be configured for the desired operational modes and formats. The operation of the control port may be completely asynchronous with respect to the audio sample rates. -
Page 39: I2C Mode
CS42518 4.7.2 C Mode In I C mode, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL. There is no CS pin. Pins AD0 and AD1 form the two least significant bits of the chip address and should be connected through a resistor to VLC or DGND as desired. -
Page 40: Interrupts
CS42518 Send stop condition, aborting write. Send start condition. Send 10011xx1(chip address & read operation). Receive acknowledge bit. Receive byte, contents of selected register. Send acknowledge bit. Send stop condition. Setting the auto increment bit in the MAP allows successive reads or writes of consecutive registers. Each byte is separated by an acknowledge bit. - Page 41 CS42518 Extensive use of power and ground planes, ground plane fill in unused areas and surface mount decou- pling capacitors are recommended. Decoupling capacitors should be as near to the pins of the CS42518 as possible. The low value ceramic capacitor should be the nearest to the pin and should be mounted on the same side of the board as the CS42518 to minimize inductance effects.
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Page 42: Register Quick Reference
CS42518 5 REGISTER QUICK REFERENCE Addr Function Chip_ID3 Chip_ID2 Chip_ID1 Chip_ID0 Rev_ID3 Rev_ID2 Rev_ID1 Rev_ID0 default p 46 Power Con- Reserved PDN_RCVR PDN_ADC PDN_DAC4 PDN_DAC3 PDN_DAC2 PDN_DAC1 trol default p 47 Functional CODEC_FM1 CODEC_FM0 SAI_FM1 SAI_FM0 ADC_SP ADC_SP DAC_DEM RCVR_DEM Mode SEL1 SEL0... - Page 43 CS42518 Addr Function Vol. Control A2_VOL7 A2_VOL6 A2_VOL5 A2_VOL4 A2_VOL3 A2_VOL2 A2_VOL1 A2_VOL0 default p 58 Vol. Control B2_VOL7 B2_VOL6 B2_VOL5 B2_VOL4 B2_VOL3 B2_VOL2 B2_VOL1 B2_VOL0 default p 58 Vol. Control A3_VOL7 A3_VOL6 A3_VOL5 A3_VOL4 A3_VOL3 A3_VOL2 A3_VOL1 A3_VOL0 default p 58 Vol.
- Page 44 CS42518 Addr Function Interrupt UNLOCK1 Reserved QCH1 DETC1 DETU1 Reserved RERR1 Mode MSB default p 64 Interrupt UNLOCK0 Reserved QCH0 DETC0 DETU0 Reserved RERR0 Mode LSB default p 64 Buffer Ctrl Reserved Reserved Reserved Reserved Reserved BSEL default p 65 RCVR CS AUX3 AUX2...
- Page 45 CS42518 Addr Function Q Subcode Frame7 Frame6 Frame5 Frame4 Frame3 Frame2 Frame1 Frame0 default p 70 Q Subcode Zero7 Zero6 Zero5 Zero4 Zero3 Zero2 Zero1 Zero0 default p 70 Q Subcode A.Minute7 A.Minute6 A.Minute5 A.Minute4 A.Minute3 A.Minute2 A.Minute1 A.Minute0 default p 70 Q Subcode A.Second7...
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Page 46: Register Description
CS42518 6 REGISTER DESCRIPTION All registers are read/write except for the I.D. and Revision Register, OMCK/PLL_CLK Ratio Register, In- terrupt Status Register, and Q-Channel Subcode Bytes and C-bit or U-bit Data Buffer, which are read only. See the following bit definition tables for bit assignment information. The default state of each bit after a power-up sequence or reset is listed in each bit description. -
Page 47: Power Control (Address 02H)
CS42518 Power Control (address 02h) Reserved PDN_RCVR PDN_ADC PDN_DAC4 PDN_DAC3 PDN_DAC2 PDN_DAC1 6.3.1 POWER DOWN RECEIVER (PDN_RCVR) Default = 0 Function: When enabled, the S/PDIF receiver and PLL will remain in a reset state. It is advised that any change of this bit be made while the DACs are muted or the power down bit (PDN) is enabled to eliminate the possibility of audible artifacts. -
Page 48: Table 6. Dac De-Emphasis
CS42518 6.4.2 SERIAL AUDIO INTERFACE FUNCTIONAL MODE (SAI_FMX) Default = 00 00 - Single-Speed Mode (4 to 50 kHz sample rates) 01 - Double-Speed Mode (50 to 100 kHz sample rates) 10 - Quad-Speed Mode (100 to 192 kHz sample rates) 11 - Reserved Function: Selects the required range of sample rates for the Serial Audio Interface port(SAI_SP). -
Page 49: Interface Formats (Address 04H)
CS42518 6.4.5 RECEIVER DE-EMPHASIS CONTROL (RCVR_DEM) Default = 0 Function: When enabled, de-emphasis will be automatically applied when emphasis is detected based on the channel status bits. The appropriate digital filter will be selected to maintain the standard 15µs/50µs digital de-emphasis filter response at the auto-detected sample rate of either 32, 44.1, or 48 kHz. If the FRC_PLL_LK bit is set to a ‘1’b, then the auto-detect sample rate feature is disabled. -
Page 50: Table 9. Adc One-Line Mode
CS42518 6.5.2 ADC ONE_LINE MODE (ADC_OLX) Default = 00 Function: These bits select which mode the ADC will use. By default one-line mode is disabled but can be se- lected using these bits. Please see Figures 14 and 15 to see the format of one-line mode 1 and one-line mode 2. -
Page 51: Misc Control (Address 05H)
CS42518 Misc Control (address 05h) Ext ADC SCLK HiZ_RMCK Reserved FREEZE FILT_SEL HPF_FREEZE CODEC_SP SAI_SP 6.6.1 EXTERNAL ADC SCLK SELECT (EXT ADC SCLK) Default = 0 Function: This bit identifies the SCLK source for the external ADCs attached to the ADCIN1/2 ports when using one line mode of operation. -
Page 52: Clock Control (Address 06H)
CS42518 6.6.6 CODEC SERIAL PORT MASTER/SLAVE SELECT (CODEC_SP M/S) Default = 0 Function: In Master mode, CX_SCLK and CX_LRCK are outputs. Internal dividers will divide the master clock to generate the serial clock and left/right clock. In Slave mode, CX_SCLK and CX_LRCK become in- puts. -
Page 53: Table 12. Omck Frequency Settings
CS42518 6.7.2 OMCK FREQUENCY (OMCK FREQX) Default = 00 Function: Sets the appropriate frequency for the supplied OMCK. OMCK Freq1 OMCK Freq0 Description 11.2896 MHz or 12.2880 MHz 16.9344 MHz or 18.4320 MHz 22.5792 MHz or 24.5760 MHz Reserved Table 12. OMCK Frequency Settings 6.7.3 PLL LOCK TO LRCK (PLL_LRCK) Default = 0... -
Page 54: Omck/Pll_Clk Ratio (Address 07H) (Read Only)
CS42518 OMCK/PLL_CLK Ratio (address 07h) (Read Only) RATIO7(2 RATIO6(2 RATIO5(2 RATIO4(2 RATIO3(2 RATIO2(2 RATIO1(2 RATIO0(2 6.8.1 OMCK/PLL_CLK RATIO (RATIOX) Default = xxxxxxxx Function: This register allows the user to find the exact absolute frequency of the recovered MCLK coming from the PLL. -
Page 55: Burst Preamble Pc And Pd Bytes (Addresses 09H - 0Ch)(Read Only)
CS42518 6.9.3 SYSTEM CLOCK SELECTION (ACTIVE_CLK) Default = x 0 - Output of PLL 1 - OMCK Function: This bit identifies the source of the internal system clock (MCLK). 6.9.4 RECEIVER CLOCK FREQUENCY (RCVR_CLKX) Default = xxx Function: The CS42518 will auto-detect the ratio between the OMCK and the recovered clock from the PLL, which is displayed in register 07h. -
Page 56: Volume Transition Control (Address 0Dh)
CS42518 6.11 Volume Transition Control (address 0Dh) Reserved SNGVOL SZC1 SZC0 AMUTE MUTE SAI_SP RAMP_UP RAMP_DN 6.11.1 SINGLE VOLUME CONTROL (SNGVOL) Default = 0 Function: The individual channel volume levels are independently controlled by their respective Volume Control registers when this function is disabled. When enabled, the volume on all channels is determined by the A1 Channel Volume Control register and the other Volume Control registers are ignored. - Page 57 CS42518 6.11.3 AUTO-MUTE (AMUTE) Default = 1 0 - Disabled 1 - Enabled Function: The Digital-to-Analog converters of the CS42518 will mute the output following the reception of 8192 consecutive audio samples of static 0 or -1. A single sample of non-static data will release the mute. Detection and muting is done independently for each channel.
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Page 58: Channel Mute (Address 0Eh)
CS42518 6.12 Channel Mute (address 0Eh) B4_MUTE A4_MUTE B3_MUTE A3_MUTE B2_MUTE A2_MUTE B1_MUTE A1_MUTE 6.12.1 INDEPENDENT CHANNEL MUTE (XX_MUTE) Default = 0 0 - Disabled 1 - Enabled Function: The Digital-to-Analog converter outputs of the CS42518 will mute when enabled. The quiescent volt- age on the outputs will be retained. -
Page 59: Mixing Control Pair 1 (Channels A1 & B1)(Address 18H)
CS42518 6.15 Mixing Control Pair 1 (Channels A1 & B1)(address 18h) Mixing Control Pair 2 (Channels A2 & B2)(address 19h) Mixing Control Pair 3 (Channels A3 & B3)(address 1Ah) Mixing Control Pair 4 (Channels A4 & B4)(address 1Bh) Px_A=B Reserved Reserved Px_ATAPI4 Px_ATAPI3... -
Page 60: Table 17. Atapi Decode
CS42518 6.15.2 ATAPI CHANNEL MIXING AND MUTING (PX_ATAPIX) Default = 01001 Function: The CS42518 implements the channel mixing functions of the ATAPI CD-ROM specification. The ATAPI functions are applied per A-B pair. Refer to Table 17 and Figure 9 for additional information. ATAPI4 ATAPI3 ATAPI2... -
Page 61: Adc Left Channel Gain (Address 1Ch)
CS42518 6.16 ADC Left Channel Gain (address 1Ch) Reserved Reserved LGAIN5 LGAIN4 LGAIN3 LGAIN2 LGAIN1 LGAIN0 6.16.1 ADC LEFT CHANNEL GAIN (LGAINX) Default = 00h Function: The level of the left analog channel can be adjusted in 1 dB increments as dictated by the Soft and Zero Cross bits (SZC[1:0]) from +15 to -15 dB. -
Page 62: Receiver Mode Control 2 (Address 1Fh)
CS42518 6.18.2 DE-EMPHASIS SELECT BITS (DE-EMPHX) Default = 00 00 - Reserved 01 - De-Emphasis for 32 kHz sample rate. 10 - De-Emphasis for 44.1 kHz sample rate. 11 - De-Emphasis for 48 kHz sample rate. Function: Used to specify which de-emphasis filter to apply when the “FORCE PLL LOCK (FRC_PLL_LK)” on page 53 is enabled. -
Page 63: Interrupt Status (Address 20H) (Read Only)
CS42518 TMUX2 TMUX1 TMUX0 Description Output from pin RXP6 Output from pin RXP7 Table 19. TXP Output Selection 6.19.2 RECEIVER MULTIPLEXER (RMUXX) Default = 000 Function: Selects which of the eight receiver inputs will be mapped to the internal receiver. RMUX2 RMUX1 RMUX0... -
Page 64: Interrupt Mask (Address 21H)
CS42518 6.20.4 D TO E U-BUFFER TRANSFER (DETU) Default = 0 Function: Indicates when the user status buffer has changed. 6.20.5 ADC OVERFLOW (OVERFLOW) Default = 0 Function: Indicates that there is an over-range condition anywhere in the CS42518 ADC signal path. 6.20.6 RECEIVER ERROR (RERR) Default = 0 Function:... -
Page 65: Channel Status Data Buffer Control (Address 24H)
CS42518 01 - Falling edge active 10 - Level active 11 - Reserved 6.23 Channel Status Data Buffer Control (address 24h) Reserved Reserved Reserved Reserved Reserved BSEL 6.23.1 DATA BUFFER SELECT (BSEL) Default = 0 0 - Data buffer address space contains Channel Status data 1 - Data buffer address space contains User data Function: Selects the data buffer register addresses to contain either User data or Channel Status data. -
Page 66: Receiver Errors (Address 26H) (Read Only)
CS42518 AUX3 AUX2 AUX1 AUX0 Description Auxiliary data is not present Auxiliary data is 1 bit long Auxiliary data is 2 bit long Auxiliary data is 3 bit long Auxiliary data is 4 bit long Auxiliary data is 5 bit long Auxiliary data is 6 bit long Auxiliary data is 7 bit long Auxiliary data is 8 bit long... - Page 67 CS42518 6.25.1 CRC ERROR (QCRC) Default = x 0 - No error 1 - Error Function: Indicates a Q-subcode data CRC error. This bit is updated on Q-subcode block boundaries. 6.25.2 REDUNDANCY CHECK (CCRC) Default = x 0 - No error 1 - Error Function: Indicates a channel status block cyclic redundancy.
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Page 68: Receiver Errors Mask (Address 27H)
CS42518 6.25.7 PARITY STATUS (PAR) Default = x 0 - No error 1 - Parity Error Function: Indicates the Parity status. This bit is updated on sub-frame boundaries. 6.26 Receiver Errors Mask (address 27h) Reserved QCRCM CCRCM UNLOCKM CONFM BIPM PARM Default = 00000000 Function:... -
Page 69: Rxp/General Purpose Pin Control (Addresses 29H To 2Fh)
CS42518 6.28 RXP/General Purpose Pin Control (addresses 29h to 2Fh) Mode1 Mode0 Polarity Function4 Function3 Function2 Function1 Function0 6.28.1 MODE CONTROL (MODEX) Default = 00 00 - RXP Input 01 - Mute Mode 10 - GPO/Overflow Mode 11 - GPO, Drive High Mode Function: RXP Input - The pin is configured as a receiver input which can then be muxed to either the TXP pin or to the internal receiver. -
Page 70: Q-Channel Subcode Bytes 0 To 9 (Addresses 30H To 39H) (Read Only)
CS42518 0 - Channel mute is not mapped to the RXPx/GPOx pin 1 - Channel mute is mapped to the RXPx/GPOx pin: RXPx/GPOx Reg Address Function4 Function3 Function2 Function1 Function0 RXP7/GPO7 M_AOUTA1 M_AOUTB1 M_AOUTA2 M_AOUTA3 M_AOUTA4 pin 42 M_AOUTB2 M_AOUTB3 M_AOUTB4 RXP6/GPO6 M_AOUTA1... -
Page 71: Parameter Definitions
CS42518 7 PARAMETER DEFINITIONS Dynamic Range The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified band width made with a -60 dBFS signal. -
Page 72: References
Digital Audio Transmission, by Clifton Sanchez.; an excellent tutorial on SCMS. It is available from the AES as preprint 3518. 6) Cirrus Logic, Techniques to Measure and Maximize the Performance of a 120 dB, 96 kHz A/D Con- verter Integrated Circuit, by Steven Harris, Steven Green and Ka Leung. Presented at the 103rd Con- vention of the Audio Engineering Society, September 1997. -
Page 73: Package Dimensions
CS42518 9 PACKAGE DIMENSIONS 64L LQFP PACKAGE DRAWING ∝ INCHES MILLIMETERS 0.55 0.063 1.40 1.60 0.002 0.004 0.006 0.05 0.10 0.15 0.007 0.008 0.011 0.17 0.20 0.27 0.461 0.472 BSC 0.484 11.70 12.0 BSC 12.30 0.390 0.393 BSC 0.398 9.90 10.0 BSC 10.10 0.461... -
Page 74: Appendix A: External Filters
CS42518 10 APPENDIX A: EXTERNAL FILTERS 10.1. ADC Input Filter The analog modulator samples the input at 6.144 MHz (internal MCLK=12.288 MHz). The digital filter will reject signals within the stopband of the filter. However, there is no rejection for input signals which are ×... -
Page 75: Appendix B: S/Pdif Receiver
CS42518 11 APPENDIX B: S/PDIF RECEIVER 11.1. Error Reporting and Hold Function The UNLOCK bit indicates whether the PLL is locked to the incoming S/PDIF data. The V bit reflects the current validity bit status. The CONF (confidence) bit indicates the amplitude of the eye pattern opening, indicating a link that is close to generating errors. -
Page 76: Channel Status Data E Buffer Access
CS42518 8-bits 8-bits From S/PDIF Received words Receiver Data Buffer Control Port Figure 27. Channel Status Data Buffer Structure 11.2.1 Channel Status Data E Buffer Access The user can monitor the incoming Channel Status data by reading the E buffer, which is mapped into the register space of the CS42518, through the control port Data Buffer. -
Page 77: Serial Copy Management System (Scms)
CS42518 11.2.2 Serial Copy Management System (SCMS) The CS42518 allows read access to all the channel status bits. For consumer mode SCMS compliance, the host microcontroller needs to read and interpret the Category Code, Copy bit and L bit appropriately. 11.3. -
Page 78: Appendix C: Pll Filter
CS42518 12 APPENDIX C: PLL FILTER The PLL has been designed to only use the preambles of the S/PDIF stream to provide lock update infor- mation to the PLL. This results in the PLL being immune to data dependent jitter effects because the S/PDIF preambles do not vary with the data. -
Page 79: External Filter Components
CS42518 12.1. External Filter Components 12.1.1 General The PLL behavior is affected by the external filter component values in the Typical Connection Diagrams. Figure 5 and Figure 6 show the recommended configuration of the two capacitors and one resistor that comprise the PLL filter. -
Page 80: Capacitor Selection
CS42518 12.1.3 Capacitor Selection The type of capacitors used for the PLL filter can have a significant effect on receiver performance. Large or exotic film capacitors are not necessary as their leads and the required longer circuit board traces add undesirable inductance to the circuit. -
Page 81: Appendix D: External Aes3/Spdif/Iec60958 Receiver Components
CS42518 13 APPENDIX D: EXTERNAL AES3/SPDIF/IEC60958 RECEIVER COMPONENTS 13.1. AES3 Receiver External Components The CS42518 AES3 receiver is designed to accept only consumer-standard interfaces. The standards call for an unbalanced circuit having a receiver impedance of 75 Ω ±5%. The connector is an RCA phono socket. -
Page 82: Appendix E: Adc Filter Plots
CS42518 14 APPENDIX E: ADC FILTER PLOTS -100 -100 -110 -110 -120 -120 -130 -130 -140 -140 0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60 Frequency (normalized to Fs) Frequency (normalized to Fs) Figure 34. Single Speed Mode Stopband Rejection Figure 35. -
Page 83: Figure 40. Double Speed Mode Transition Band (Detail)
CS42518 ‘ 0.10 0.08 0.05 0.03 0.00 -0.03 -0.05 -0.08 -0.10 0.40 0.43 0.45 0.48 0.50 0.53 0.55 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 Frequency (normalized to Fs) Frequency (normalized to Fs) Figure 40. Double Speed Mode Transition Band (Detail) Figure 41. -
Page 84: Appendix F: Dac Filter Plots
CS42518 15 APPENDIX F: DAC FILTER PLOTS 0.42 0.44 0.46 0.48 0.52 0.54 0.56 0.58 Frequency(normalized to Fs) Frequency(normalized to Fs) Figure 46. Single Speed (fast) Stopband Rejection Figure 47. Single Speed (fast) Transition Band 0.02 0.015 0.01 0.005 0.005 0.01 0.015 0.02... -
Page 85: Figure 52. Single Speed (Slow) Transition Band (Detail)
CS42518 0.02 0.015 0.01 0.005 0.005 0.01 0.015 0.02 0.05 0.15 0.25 0.35 0.45 0.45 0.46 0.47 0.48 0.49 0.51 0.52 0.53 0.54 0.55 Frequency(normalized to Fs) Frequency(normalized to Fs) Figure 52. Single Speed (slow) Transition Band (detail) Figure 53. Single Speed (slow) Passband Ripple 0.42 0.44 0.46... -
Page 86: Figure 58. Double Speed (Slow) Stopband Rejection
CS42518 Frequency(normalized to Fs) Frequency(normalized to Fs) Figure 58. Double Speed (slow) Stopband Rejection Figure 59. Double Speed (slow) Transition Band 0.02 0.015 0.01 0.005 0.005 0.01 0.015 0.02 0.45 0.46 0.47 0.48 0.49 0.51 0.52 0.53 0.54 0.55 0.05 0.15 0.25 0.35... -
Page 87: Figure 64. Quad Speed (Fast) Transition Band (Detail)
CS42518 0.15 0.05 0.05 0.15 0.05 0.15 0.25 0.45 0.46 0.47 0.48 0.49 0.51 0.52 0.53 0.54 0.55 Frequency(normalized to Fs) Frequency(normalized to Fs) Figure 64. Quad Speed (fast) Transition Band (detail) Figure 65. Quad Speed (fast) Passband Ripple Frequency(normalized to Fs) Frequency(normalized to Fs) Figure 66.