Cirrus Logic CS42518-CQZ Instructions Manual page 6

Figure 52. Single Speed (slow) Transition Band (detail) ............................................................... 85
Figure 53. Single Speed (slow) Passband Ripple ......................................................................... 85
Figure 54. Double Speed (fast) Stopband Rejection ..................................................................... 85
Figure 55. Double Speed (fast) Transition Band ........................................................................... 85
Figure 56. Double Speed (fast) Transition Band (detail) ............................................................... 85
Figure 57. Double Speed (fast) Passband Ripple ......................................................................... 85
Figure 58. Double Speed (slow) Stopband Rejection ................................................................... 86
Figure 59. Double Speed (slow) Transition Band.......................................................................... 86
Figure 60. Double Speed (slow) Transition Band (detail).............................................................. 86
Figure 61. Double Speed (slow) Passband Ripple........................................................................ 86
Figure 62. Quad Speed (fast) Stopband Rejection ....................................................................... 86
Figure 63. Quad Speed (fast) Transition Band.............................................................................. 86
Figure 64. Quad Speed (fast) Transition Band (detail).................................................................. 87
Figure 65. Quad Speed (fast) Passband Ripple............................................................................ 87
Figure 66. Quad Speed (slow) Stopband Rejection ...................................................................... 87
Figure 67. Quad Speed (slow) Transition Band ............................................................................ 87
Figure 68. Quad Speed (slow) Transition Band (detail) ................................................................ 87
Figure 69. Quad Speed (slow) Passband Ripple .......................................................................... 87
LIST OF TABLES
Table 1. Revision History ...................................................................................................................... 6
Table 2. Common OMCK Clock Frequencies...................................................................................... 26
Table 3. Common PLL Output Clock Frequencies ............................................................................. 26
Table 4. Slave Mode Clock Ratios....................................................................................................... 27
Table 5. Serial Audio Port Channel Allocations ................................................................................... 27
Table 6. DAC De-Emphasis................................................................................................................. 48
Table 7. Receiver De-Emphasis .......................................................................................................... 49
Table 8. Digital Interface Formats........................................................................................................ 49
Table 9. ADC One-Line Mode ............................................................................................................. 50
Table 10. DAC One-Line Mode ........................................................................................................... 50
Table 11. RMCK Divider Settings ........................................................................................................ 52
Table 12. OMCK Frequency Settings .................................................................................................. 53
Table 13. Master Clock Source Select ................................................................................................ 53
Table 14. AES Format Detection ......................................................................................................... 54
Table 15. Receiver Clock Frequency Detection .................................................................................. 55
Table 16. Example Digital Volume Settings......................................................................................... 58
Table 17. ATAPI Decode ..................................................................................................................... 60
Table 18. Example ADC Input Gain Settings....................................................................................... 61
Table 19. TXP Output Selection .......................................................................................................... 62
Table 20. Receiver Input Selection ...................................................................................................... 63
Table 21. Auxiliary Data Width Selection............................................................................................. 66
Table 22. PLL External Component Values......................................................................................... 79
Release Date
A1 December 2002
PP1 August 2003
PP2 August 2003
PP3 March 2004
PP4 July 2004
6
Table 1. Revision History
Advance Release
Preliminary Release
- Added Revision History table.
- Updated registers 6.7.4 and 6.7.5 on p 53.
Correct typo in document title
Add lead free parts
Changes
CS42518